Second International Workshop on

Network on Chip Architectures

To be held in conjunction with the
42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42)
December 12, 2009
New York City, USA

Proceedings and Special issue
The proceedings of NoCArc 2009 will be published in the ACM Digital Library and in the IEEE Xplore	Authors of selected papers will be invited to submit an extended version of their work to contribute to a special issue of the Microprocessors and Microsystems Journal (MICPRO)

Index

• General Information
• Areas of Interest
• Submission Guidelines
• Important Dates
• Workshop Organizers
• Program Committee
• Program (and slides of the presentations NEW)
• Proceedings NEW
• Photos NEW
• Previous edition of the Workshop (NoCArc 2008)

General Information

The continuous reduction in the time-to-market required by the telecommunications, multimedia and consumer electronics market makes full-custom design inappropriate and has led to the definition of design methodologies based on the reuse of Intellectual Properties (IPs, or cores). This has caused an increment in complexity and heterogeneity of single chip based embedded systems. In the many cores era, as the number of cores on a System-on-Chip (SoC) multiplies, on-chip communication solutions are evolving in order to support the new inter-core communication demands. Now-a-days it is recognized that traditional bus-based interconnect architectures have hit their scalability limit, and are no longer adequate for deep-sub-micron (DSM) technologies. The heterogeneity of the cores to be interconnected along with reliability and power-related issues and the need of introducing some kind of floorplan-awareness into each level of the design flow, represent additional issues which have to be addressed. Network-on-Chip (NoC) is generally viewed as the ultimate solution for the design of modular and scalable communication architectures, and provides inherent support to the integration of heterogeneous cores through the standardization of the network boundary. This workshop is focused on issues related to design, analysis and testing of on-chip networks.

Areas of Interest

The topics of specific interest for the workshop include, but are not limited to:

• Topologies Selection and Synthesis for NoCs and MPSoCs
• Routing algorithms and Router Micro-architectures
• Guaranteed Throughput and Real Time on-chip communication
• Mapping of cores to NoC slots
• Power and energy issues
• Fault tolerance and reliability issues
• Memory Architectures for NoC
• Dynamic on-chip network reconfiguration
• Modeling and evaluation of on-chip networks
• Design space exploration and tradeoff analysis
• On-chip interconnection network simulators and emulators
• Verification, debug and test of NoC
• Emerging technologies and new design paradigms
• Industrial case studies of SoC designs using the NoC paradigm

The goal of the workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.

Submission Guidelines

Both research and application-oriented papers are welcome. All papers should be submitted electronically by EasyChair. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author.

Papers must be formatted in accordance to the ACM style. ACM Word or LaTeX style templates are available here. In addition, Authors should apply ACM Computing Classification categories and terms. In order to be published, accepted papers must show a bibliographic strip containing the copyright statement (details).

Submissions must be limited to 6 pages. Papers deviating significantly from these paper size and formatting rules may be rejected without review. If the authors wish a blind review to be performed, then the author's name and affiliation should be omitted in the submitted paper. In case of any questions please contact the workshop organizers.

Important Dates

Workshop Organizers

• Maurizio Palesi, <mpalesi [at] diit.unict.it>
  Dipartimento di Ingegneria Informatica e delle Telecomunicazioni
  University of Catania, Italy
   
• Shashi Kumar, <Shashi.Kumar [at] jth.hj.se>
  Department of Electronics and Computer Engineering
  School of Engineering, Jönköping University, Sweden

Program Committee

• Federico Angiolini, iNoCs, Switzerland
• Giuseppe Ascia, University of Catania, Italy
• Davide Bertozzi, University of Ferrara, Italy
• Giorgos Dimitrakopoulos, FORTH, Greece
• Natalie Enright Jerger, University of Toronto, Canada
• Manoj Singh Gaur, Malaviya National Institute of Technology, India
• José Flich Cardo, Universidad Politécnica de Valencia, Spain
• Martti Forsell, VTT, Finland
• Ahmed Hemani, Royal Institute of Technology, Sweden
• Yuho Jin, University of Southern California, USA
• Anshul Kumar, Indian Institute of Technology (Delhi), India
• Shashi Kumar, Jönköping University, Sweden
• Marcello Lajolo, NEC Laboratories America, NJ, USA
• Zhonghai Lu, Royal Institute of Technology, Sweden
• Radu Marculescu, Carnegie Mellon University, USA
• Juan Manuel Orduña Huertas, Universidad de Valencia, Spain
• Gianluca Palermo, Politecnico di Milano, Italy
• Maurizio Palesi, University of Catania, Italy
• Davide Patti, University of Catania, Italy
• Partha P. Pande, Washington State University, USA
• Carlo Pistritto, STMicroelectronics, Italy
• Alberto Scandurra, STMicroelectronics, Italy
• Virendra Singh, Indian Institute of Science, Bangalore, India
• Tor Skeie, University of Oslo, Norway
• Christof Teuscher, Portland State University, USA
• Mei Yang, University of Nevada, USA
• Vittorio Zaccaria, Politecnico di Milano, Italy

Program