Maurizio Palesi

Associate Professor of Computer Engineering (cv, google scholar)
University of Catania, Italy
maurizio.palesi@dieei.unict.it

Short bio

Maurizio Palesi is an Associate Professor in Computer Engineering at University of Catania, Italy. His research activity is focused in the area of em- bedded systems with particular emphasis on single-chip implementations based on the network-on-chip design paradigm. He has served as Guest Editor of 30 special issues in top-level journals. He has served as General Chair and TPC Co-Chair in several international conferences and workshops. He serves as Associate Editor in 15 international journals. He has been recipient of the best paper award at the DATE 2011 and the HiPEAC paper award 2014. He is member of the HiPEAC and IEEE Senior Member.

Publications

Books

  1. Maurizio Palesi and Masoud Daneshtalab. Routing Algorithms in Networks-on-Chip. Springer. ISBN 978-1-4614-8273-4

Journals

  1. Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Andrea Mineo, Giuseppe Ascia, Vincenzo Catania. "DNN Model Compression for IoT Domain Specific Hardware Accelerators," in IEEE Internet of Things Journal, doi: 10.1109/JIOT.2021.3111723.

  2. Nizar Dahir, Ammar Karkar, Maurizio Palesi, Terrence Mak, Alex Yakovlev. Power Density Aware Application Mapping in Mesh-Based Network-on-Chip Architecture: An Evolutionary Multi-Objective Approach. Integration, the VLSI Journal, Elsevier, vol. 81, 2021.

  3. Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi. Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty. IEEE Transactions on Computers, vol. 70, no. 6, pp. 892-905, 2021.

  4. Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi. Revising NoC in Future Multi-Core based Consumer Electronics for Performance. IEEE Consumer Electronics Magazine, doi: 10.1109/MCE.2021.3062001.

  5. Lahdhiri, H.; Lorandel, J.; Monteleone, S.; Bourdel, E.; Palesi, M. Framework for Design Exploration and Performance Analysis of RF-NoC Manycore Architecture. J. Low Power Electron. Appl. 2020, 10, 37.

  6. D. Deb, J. Jose, M. Palesi. COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC based MPSoCs. ACM Transactions on Design Automation of Electronic Systems, 26(326), Feb. 2021.

  7. S. Xiao, X. Wang, M. Palesi, A. K. Singh, L. Wang and T. Mak. On Performance Optimization and Quality Control for Approximate-communication-enabled Networks-on-Chip. IEEE Transactions on Computers, 70(11), pp. 1817-1830, Nov. 2021.

  8. S. Morteza Nabavinejad, M. Baharloo, K. C. Chen, M. Palesi, T. Kogel, and M. Ebrahimi. An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2020.

  9. S. Mnejja, Y. Aydi, M. Abid, S. Monteleone, V. Catania, M. Palesi, D. Patti. Delta Multi-stage Interconnection Networks for Scalable Wireless On-Chip Communication. Accepted in MDPI Electronics Journal.

  10. V. Catania, S. Monteleone, M. Palesi, D. Patti. Impact of Users’ Beliefs in Text-Based Linguistic Interaction. IEEE Access vol. 8, pp. 46861-46867, 2020.

  11. G. Ascia, V. Catania, S. Monteleone, M. Palesi, D. Patti, J. Jose, V. M. Salerno. Exploiting Data Resilience in Wireless Network-on-ChipArchitectures. ACM Journal on Emerging Technologies in Computing Systems, 16(2), 2020.

  12. A. Monemi, F. Khunjush, M. Palesi, H. Sarbazi-Azad. An Enhanced Dynamic Weighted Incremental Technique for QoS Support in NoC. Accepted for publication in ACM Transactions on Parallel Computing.

  13. D. Deb, J. Jose, M. Palesi. ECAP:Energy Efficient CAching for Prefetch Blocks in Tiled Chip MultiProcessors. IET Computers & Digital Techniques. 2019.

  14. S. Khan, S. Anjum, U. A. Gulzari, M. K. Afzal, F. Ishmanov, M. Palesi. An Optimized Hybrid Algorithm in term of Energy and Performance for Mapping Real Time Workloads on 2D based On-Chip Networks. Applied Intelligence. Vol. 48, Issue 12, pp. 4792--4804, December 2018.

  15. M. Tang, J. Lin, M. Palesi. The Suboptimal Routing Algorithm for 2D Mesh Network. IEEE Transactions on Computers. Vol. 67, no. 5, pp. 704-716, May 2018.

  16. V. Catania, A. Mineo, S. Monteleone, M. Palesi, D. Patti. Improving Energy Efficiency in Wireless Network-on-Chip Architectures. ACM Journal on Emerging Technologies in Computing Systems. Volume 14 Issue 1, March 2018.

  17. A. Monemi, C. Y. Ooi, M. Palesi, M. N. Marsonoa. Ping-Lock Round Robin Arbiter. Microelectronics Journal, Microelectronics Journal. Vol. 63, No. 1, pp. 81-93, May 2017.

  18. A. Monemi, J. W. Tang, M. Palesi, M. N. Marsono. ProNoC: A Low Latency Network-on-Chip based Many-Core System-on-Chip Prototyping Platform., Microprocessors and Microsystems, Elsevier, 54, pp. 60-74, 2017.

  19. M. Tang, X. Lin and M. Palesi. The Repetitive Turn Model for Adaptive Routing. IEEE Transactions on Computers, vol. 66, no. 1, pp. 138-146, Jan. 2017.

  20. V. Catania, A. Mineo, S. Monteleone, M. Palesi, D. Patti. Cycle-Accurate Network on Chip Simulation with Noxim. ACM Transactions on Modeling and Computer Simulation. Vol. 27, No. 1, Aug. 2016.

  21. A. Mineo, M. Palesi, G. Ascia, V. Catania. Exploiting Antenna Directivity in Wireless NoC Architectures. Microprocessors and Microsystems Elsevier. Vol. 43, pp. 59-66, June 2016.

  22. A. Mineo, M. Palesi, G. Ascia, P. P. Pande, V. Catania. On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 11, pp. 1769-1782, Nov. 2016.

  23. M. Palesi, M. Collotta, M. Daneshtalab and P. Bose. Special Section on Energy Efficient Methods and Systems in the Emerging Cloud Computing Era. Journal of Computer and System Sciences. 82(2), March 2016.

  24. M. Tang, X. Lin and M. Palesi. Local Congestion Avoidance in Network-on-Chip. IEEE Transactions on Parallel and Distributed Systems. 27(7), pp. 2062-2073, July 2016.

  25. A. Mineo, M. Palesi, G. Ascia, V. Catania. Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures. IEEE Transactions on Very Large Scale Integration Systems. 2015. 24(4), pp. 1535-1545, April 2016.

  26. M. S. Rusli, A. Mineo, M. Palesi, G. Ascia, V. Catania, O. C. Yee, M. N. Marsono. A closed loop power manager for transmission power control in wireless network-on-chip architectures. Jurnal Teknologi, 75(1), pp. 207-214, July 2015.

  27. N. Jafarzadeh, M. Palesi, S. Eskandari, S. Hessabi, A. Afzali-Kusha. Low Energy yet Reliable Data Communication Scheme for Networks on Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015. 34(12), pp. 1892-1904, Dec. 2015.

  28. M. Tang, X. Lin, M. Palesi. Routing Pressure: A Channel-Related and Traffic-Aware Metric of Routing Algorithm. IEEE Transactions on Parallel and Distributed Systems. 26(3), March 2015.

  29. M. Palesi, M. Collotta, A. Mineo, V. Catania. An Efficient Radio Access Control Mechanism for Wireless Network-on-Chip Architectures. Journal of Low Power Electronics and Applications. 5(2) pp. 38-56, 2015.

  30. M. Palesi, D. Patti, G. Ascia, D. Panno, V. Catania. Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip. Journal of Computer Science, Science Publications, 11(3), pp. 552-566, 2015.

  31. M. Tang, X. Lin, M. Palesi. An Offline Method for Designing Adaptive Routing Based on Pressure Model. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 34(2), Feb. 2015, pp. 307-320.

  32. X. Wang, M. Yang, Y. Jiang, M. Daneshtalab, M. Palesi, T. Mak. On Self-tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation. ACM Transactions on Embedded Computing Systems. 13(2), Jan. 2014.

  33. N. Jafarzadeh, M. Palesi, A. Khademzadeh, A. Afzali-Kusha. Data Encoding Techniques for Reducing Energy Consumption in Networks on Chip. IEEE Transactions on Very Large Scale Integration (VLSI). 22(3), Mar. 2014.

  34. M. Palesi, Todor Stefanov. Editorial: Special Section on ESTIMedia’13. ACM Transactions on Embedded Computing Systems, Vol. 13, No. 3s, Article 110, Publication date: March 2014.

  35. M. Daneshtalab, M. Palesi, J. Plosila, A. Hemani. Editorial of the Special issue on Many-core Embedded Systems. Elsevier Microprocessors and Microsystems, 38(6), Aug. 2014.

  36. X. Wang, M. Yang, Y. Jiang, M. Palesi, P. Liu, T. Mak, N. Bagherzadeh.Efficient multicast schemes for 3-D Networks-on-Chip. Journal of Systems Architecture, 59(9), Oct. 2013, pp. 693–708.

  37. F. Shen, M. Palesi, M. Yang. Guest Editors Introduction to the Special Issue on Novel On-Chip Parallel Architectures and Software Support. Parallel Computing Journal, September 2013.

  38. T. Mak, M. Palesi, M. Daneshtalab. Editorial of the Special Issue on Emerging On-Chip Networks and Architectures. IET Computers & Digital Techniques, 2013. doi: 10.1049/iet-cdt.2013.0144

  39. X. Wang, P. Liu, M. Yang, M. Palesi, Y. Jiang, M. C. Huang. Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip. Springer, Journal of Computer Science and Technology, 28(1), pp. 54-71, January 2013.

  40. J.-J. Chen, M. Palesi. Introduction to the Special Section on ESTIMedia’12. ACM Transactions on Embedded Computing Systems, Vol. 12, No. 1s, Article 32, Publication date: March 2013.

  41. M. Palesi, R. Tornero, J. M. Orduna, D. Panno, V. Catania. Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip: A Multi-objective Evolutionary-based Approach. Journal of Universal Computer Science. 18(7), pp. 937-969.

  42. D. Patti, A. Spadaccini, M. Palesi, F. Fazzino, V. Catania. Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator. IEEE Transactions on Education. 55(3), pp. 406-411, Aug 2012.

  43. R. Al-Dujaily, T. Mak, F. Xia, A. Yakovlev, M. Palesi. Embedded Transitive Closure Network for Run-Time Deadlock Detection in Networks-on-Chip. IEEE Transactions on Parallel and Distributed Systems, 23(7), pp. 1205-1215, July 2012.

  44. F. Shen, M. Yang, M. Palesi: Guest Editors' Introduction to the Special Issue on Emerging Computing Architectures and Systems. Computers & Electrical Engineering 38(3): 722-723, 2012.

  45. M. Palesi, S. Kumar, R. Marculescu. Editorial of the Special Issue on Network on Chip Architectures and Design Methodologies. Elsevier Microprocessors and Microsystems Journal. Jan 2011.

  46. M. Palesi, G. Ascia, F. Fazzino, V. Catania. Data Encoding Schemes in Networks on Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(5), May 2011.

  47. M. Yang, Y. Jiang, P. Liu, M. Palesi. Editorial of the Special Issue on Power-Efficient, High Performance General Purpose and Application Specific Computing Architectures. International Journal of High Performance Systems Architecture. 2(3/4), 2010.

  48. G. Ascia, V. Catania, A. G. Di Nuovo, M. Palesi, D. Patti. Performance Evaluation of Efficient Multi-Objective Evolutionary Algorithms for Design Space Exploration of Embedded Computer Systems. Applied Soft Computing, 11(1), pp. 382-398, January 2011.

  49. M. Palesi, S. Kumar, V. Catania. Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(3), pp. 426-440, March 2010.

  50. M. Palesi, S. Kumar, V. Catania. Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms. Computers & Digital Techniques, IET, Vol. 3, No. 5. (11 August 2009), pp. 413-429.

  51. M. Palesi, R. Holsmark, S. Kumar, V. Catania. Application Specific Routing Algorithms for Networks on Chip. IEEE Transactions on Parallel and Distributed Systems, 20(3), pp. 316-330, March 2009.

  52. A. Mejia, M. Palesi, J. Flich, S. Kumar, P. Lopez, R. Holsmark and J. Duato. Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. IEEE Transactions on on Very Large Scale Integration Systems, 17(3), pp. 356-369, March 2009.

  53. G. Ascia, V. Catania, M. Palesi, D. Patti. Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE Transactions on Computers, 57(6), pp. 809-820, June 2008.

  54. V. Catania, M. Palesi, D. Patti. Reducing Complexity of Multi-objective Design Space Exploration in VLIW-based Embedded Systems. ACM Transactions on Architecture and Code Optimization, 5(2), pp.11:1--11:33, Aug. 2008.

  55. V. Catania, M. Palesi, D. Patti. Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-objective Scenario. Journal of Circuits Systems and Computers, 16(5), pp. 819-846, Oct. 2007.

  56. R. Holsmark, M. Palesi, S. Kumar. Deadlock free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions. Journal of Systems Architecture, 54/3-4 (2008) pp. 427-440.

  57. D. Bertozzi, S. Kumar, M. Palesi. Networks-on-Chip: Emerging Research Topics and Novel Ideas. VLSI Design, vol. 2007, Article ID 26454, doi:10.1155/2007/26454.

  58. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. Efficient Design Space Exploration for Application Specific Systems-on-a-Chip. Journal of Systems Architecture, 53(10), pp. 733-750, Oct. 2007.

  59. G. Ascia, V. Catania, M. Palesi. A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. Journal of Universal Computer Science, 12(4):370--394, 2006.

  60. G. Ascia, V. Catania, M. Palesi. Mapping Cores on Network-on-Chip. International Journal of Computational Intelligence Research (IJCIR), ISSN 0972-9836, 1(1-2):109--126, 2005.

  61. G. Ascia, V. Catania, M. Palesi, and A. Parlato. Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach. IEE Proceeding on Computers & Digital Techniques, 152(6):756--764, November 2005.

  62. G. Ascia, V. Catania, and M. Palesi. A Multi-objective Genetic Approach for System-level Exploration in Parameterized Systems-on-a-chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(4):635--645, April 2005.

  63. G. Ascia, V. Catania, and M. Palesi. A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms. IEEE Transactions on Evolutionary Computation, 8(2):329--346, August 2004.

  64. G. Ascia, V. Catania, M. Palesi, and D.Sarta. An instruction-level power analysis model with data dependency. VLSI Design, 12(2):245--273, 2001.

Book Chapters

  1. M. Daneshtalab, M. Palesi. Basic Concepts on On-Chip Networks. In Routing Algorithms in Networks-on-Chip. Springer. 2013

  2. R. Al-Dujaily, T. Mak, F. Xia, A. Yakovlev, and M. Palesi. Run-Time Deadlock Detection. In Routing Algorithms in Networks-on-Chip. Springer. 2013

  3. M. Palesi, R. Holsmark, S. Kumar, and V. Catania. Application Specific Routing Algorithms for Low Power Network on Chip Design. Low Power Networks-on-Chip, Springer.

  4. G. Ascia, V. Catania, A. G. Di Nuovo, M. Palesi, and D. Patti. Computational Intelligence to Speed-Up Multi-Objective Design Space Exploration of Embedded Systems. Multi-Objective Optimization in Computational Intelligence: Theory and Practice. Lam Thu Bui (editor), Sameer Alam (editor), Chapter X, pp. 265-299, 2008.

  5. G. Ascia, V. Catania, and M. Palesi. An evolutionary approach for Pareto-optimal configurations in SOC platforms. In Kluwer Academic Pulishers, editor, SOC Design Methodologies, 2002.

  6. G. Ascia, V. Catania, and M. Palesi. Tuning methodologies for parameterized systems design. In Kluwer Academic Publishers, editor, System on Chip for Realtime Systems, 2002.

Conferences

  1. E. Russo, M. Palesi, S. Monteleone, D. Patti, G. Ascia and V. Catania, "LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation," 2021 IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, 2021.

  2. G. Ascia, V. Catania, A. Mineo, S. Monteleone, M. Palesi, and D. Patti. Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression. IEEE/ACM International Symposium on Networks-on-Chip. Sep. 24-25, 2020.

  3. H. Lahdhiri, M. Palesi, S. Monteleone, D. Patti, G. Ascia, J. Lorandel, E. Bourdel and V. Catania. DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators. Euromicro Conference on Digital System Design, August 26 – 28, 2020, Virtual Conference, Portorož, Slovenia.

  4. J. Lorandel, H. Lahdhiri, E. Bourdel, S. Monteleone and M. Palesi. Efficient Compression Technique for NoC-based Deep Neural Networks Accelerators. Euromicro Conference on Digital System Design, August 26 – 28, 2020, Virtual Conference, Portorož, Slovenia.

  5. V. Catania, A. Mineo, M. Palesi, D. Patti. Cloud-Based Energy Efficient Scheme for Sigfox Monarch as Asset Tracking Service. Accepted for publication in IEEE COINS 2020.

  6. A. Das, A. Kumar, J. Jose, M. Palesi. Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-Processors, accepted for publication in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020.

  7. G. Ascia, V. Catania, J. Jose, S. Monteleone, M. Palesi, D. Patti. Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression. Heterogeneity in Computing Workshop (collocated with IPDPS 2020). May 18 - 22, 2020, New Orleans, Louisiana USA.

  8. S. Xiao, X. Wang, M. Palesi, A. K. Singh, T. Mak. ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip. DATE 2019.

  9. Dipika Deb, John Jose and Maurizio Palesi. Performance Enhancement of Caches in TCMPs using Near Vicinity Prefetcher. Proceedings of the 32nd IEEE International Conference on VLSI Design (VLSID), 2019.

  10. Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti and John Jose. Approximate Wireless Networks-on-Chip. Conference on Design of Circuits and Integrated Systems. Lyon, France, November 14-16, 2018.

  11. A. Das, S. Babu, J. Jose, S. Jose, M. Palesi. Critical Packet Prioritisation by Slack-Aware Re-routing in On-Chip Networks. 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018), October 4 – 5, 2018, Torino, Italy.

  12. S. Z. Sleeba, J. Jose, M. Palesi, R. K. James, M. Nair. Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip. 26th IFIP/IEEE International Conference on Very Large Scale Integration. Verona, October 8-10, 2018, Verona, Italy.

  13. S. Biondi, V. Catania, S. Monteleone, M. Palesi, D. Patti. smARTworks: A Multi-sided Context-aware Platform for the Smart Museum. Int. Joint Conference on Pervasive and Embedded Computing and Communication Systems (PECCS 2018). 29-30 July, 2018, Porto, Portugal.

  14. V. Catania, S. Monteleone, M. Palesi, D. Patti. Packetization of Shared-Memory Traces for Message Passing Oriented NoC Simulation. ISC High Performance. June 24-28, 2018, Frankfurt, Germany.

  15. G. Ascia, V. Catania, S. Monteleone, M. Palesi, D. Patti and J. Jose. Improving energy consumption of NoC based architectures through approximate communication. Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro, 2018, pp. 1-4.

  16. M. S. Rusli, A. Lit, M. N. Marsono, M. Palesi. Adaptive Packet Relocator in Wireless Network-on-Chip (WiNoC). Asia Simulation Conference on Modeling, Design and Simulation of Systems, AsiaSim 2017, Melaka, Malaysia, August 27 – 29, 2017.

  17. E. Moréac, J. Laurent, P. Bomel, A. Rossi, E. Boutillon, A. Mineo and M. Palesi. Energy Aware Networks-on-Chip Cortex Inspired Communication. Accepted in International Symposium on Power and Timing Modeling, Optimization & Simulation, (PATMOS). Sept. 25-27, 2017, Thessaloniki, Greece.

  18. Alireza Monemi, Chia Yee Ooi, Maurizio Palesi, and Muhammad Nadzir Marsono. Low latency network-on-chip router using static straight allocator. In Proceedings of 3rd International Conference on Information Technology, Computer and Electrical Engineering, ICITACEE’16. IEEE, 2016.

  19. Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono, and Maurizio Palesi. Improved flow control for minimal fully adaptive routing in 2D mesh NoC. In Proceedings of the 9th International Workshop on Network on Chip Architectures, NoCArc’16, pages 9–14. ACM, 2016.

  20. A. Rezaei, M. Daneshtalab, M. Palesi, D. Zhao. Efficient Congestion-Aware Scheme for Wireless on-Chip Networks. 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP). 17-19 Feb. 2016.

  21. V. Catania, A. Mineo, S. Monteleone, M. Palesi, D. Patti. Improving the Energy Efficiency of Wireless Network on Chip Architectures through Online Selective Buffers and Receivers Shutdown. IEEE Consumer Communications and Networking Conference. Las Vegas, 9-12 Jan. 2016.

  22. V. Catania, A. Mineo, S. Monteleone, M. Palesi, D. Patti. Noxim: An Open, Extensible and Cycle-accurate Network on Chip Simulator. IEEE International Conference on Application-specific Systems, Architectures and Processors 2015 takes place July 27-29, 2015 in Toronto, Canada.

  23. A. Mineo, M. S. Rusli, M. Palesi, G. Ascia, V. Catania, and M. N. Marsono. A Closed Loop Transmitting Power Self-Calibration Scheme for Energy Efficient WiNoC Architectures. Design Automation and Test in Europe (DATE 2015). Grenoble, France, March 9-12, 2015.

  24. M. Fattah, M. Palesi, P. Liljeberg, H. Tenhunen. SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems. Design Automation Conference (DAC 2014). DAC 2014. June 1-5, 2014.

  25. A. Mineo, M. Palesi, G. Ascia, V. Catania. An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs. Design Automation and Test in Europe (DATE 2014). Dresden, Germany, March 24-28, 2014.

  26. X. Wang, B. Zhao, T. Mak, M. Yang, Y. Jiang, M. Daneshtalab, M. Palesi. Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model. Design Automation and Test in Europe (DATE 2014). Dresden, Germany, March 24-28, 2014.

  27. A. Mineo, M. S. Rusli, M. Palesi, G. Ascia, V. Catania, and M. N. Marsono. A Closed Loop Control based Power Manager for WiNoC Architectures. International Workshop on Manycore Embedded Systems (MES 2014). June 15 2014, Minneapolis, MN, USA.

  28. M. Masi, A. Mineo, M. Palesi, G. Ascia, V. Catania. Low Energy Mapping Techniques under Reliability and Bandwidth Constraints. 11th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2013), Zhangjiajie, China, November 13-15, 2013.

  29. A. Mineo, M. Palesi, G. Ascia, V. Catania. Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. EUROMICRO DSD/SEAA 2013, Santander, Spain, September 4-6, 2013.

  30. G. Ascia, M. Palesi, V. Catania. An adaptive output selection function based on a fuzzy rule base system for Network on Chip. EUROMICRO DSD/SEAA 2013, Santander, Spain, September 4-6, 2013.

  31. A. Mineo, M. Palesi, G. Ascia, V. Catania. NoC Links Energy Reduction through Link Voltage Scaling. 13th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), Samos, Greece, July 15–18, 2013.

  32. X. Wang, T. Mak, M. Yang, Y. Jiang, M. Daneshtalab, M. Palesi. On Self-Tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation. To be presented at 7th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), April 2013, Tempe, Arizona.

  33. M. Ebrahimi, M. Daneshtalab, F. Farahnakian, P. Liljeberg, J. Plosila, M. Palesi, and H. Tenhunen, "HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks," in Proceedings of 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 19-26, May. 2012, Denmark.

  34. D. Patti, A. Spadaccini, M. Palesi, F. Fazzino, and V. Catania. Improving the Teaching Effectiveness in an Introductory Computer Architecture Course. International Conference on Computational Intelligence and Software Engineering, 2011.

  35. X. Wang, M. Palesi, M. Yang, Y. Jiang, M. C. Huang, P. Liu. Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip. Lecture Notes in Computer Science, vol. 6985, Network and Parallel Computing Conference, 2011.

  36. X. Wang, M. Palesi, M. Yang, Y. Jiang, M. C. Huang, P. Liu. Low Latency and Energy Efficient Multicasting Schemes for 3D NoC-based SoCs. VLSI System on Chip. October 2011, Kowloon, Hong Kong, China.

  37. D. Salemi, M. Palesi, V. Catania. Power-Aware Selection Policy for Networks on Chip. 6th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS'11). 6-8 APril 2011, Athens, Greece.

  38. Al-Dujaily, T. Mak, F. Xia, A. Yakovlev, M. Palesi. Run-time Deadlock Detection in Networks-on-Chip using Coupled Transitive Closure Networks. Design Automation and Test in Europe (DATE 2011). 14-18 March 2011, Grenoble, France. Best Paper Award

  39. R. Holsmark, S. Kumar, M. Palesi. A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms. 4th Workshop on Highly Parallel Processing on a Chip (HPPC 2010), August 31, 2010, Ischia - Naples, Italy.

  40. M. Palesi, R. Holsmark, X. Wang, S. Kumar, M. Yang, Y. Jiang, V. Catania. A Novel Mechanism to Guarantee In-Order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. 13th Euromicro Conference On Digital System Design Architectures, Methods and Tools Lille, France, 1-3 September, 2010.

  41. M. Palesi, R. Holsmark, X. Wang, S. Kumar, M. Yang, Y. Jiang, V. Catania. An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip. 4th Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, held in conjunction with the: 5th International Conference on High Performance Embedded Architectures and Compilers, Pisa, Italy, January 24, 2010.

  42. M. Palesi and S. Kumar. Message from the Chairs. 2nd International Workshop on Network on Chip Architectures, held in conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Dec 12, 2009, New York, New York, USA.

  43. G. Ascia, V. Catania, F. Fazzino, M. Palesi. An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip. IEEE International Conference on Computer Engineering and Systems, 14-16 Dec 2009, Cairo, Egypt.

  44. V. Catania, G. De Francisci Morales, A. G. Di Nuovo, M. Palesi, D. Patti. An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures. 12th Euromicro Conference on Digital System Design, 27-29 Aug 2009, Patras, Greece.

  45. M. Palesi, F. Fazzino, G. Ascia, V. Catania. Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. 12th Euromicro Conference on Digital System Design, 27-29 Aug 2009, Patras, Greece.

  46. R. Tornero, V. Sterrantino, M. Palesi, J. M. Orduna. A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip. IEEE/ACM International Symposium on Parallel & Distributed Processing, 25-28 May, 2009, Rome, Italy.

  47. R. Holsmark, M. Palesi, S. Kumar, A. Mejia. HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip. 3rd ACM/IEEE International Symposium on Networks on Chip. May 10-13, 2009, San Diego, CA

  48. D. Frazzetta, G. Dimartino, M. Palesi, S. Kumar, V. Catania. Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. 11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 18-25, Sep. 3-5, 2008, Parma, Italy.

  49. V. Catania, G. De Francisci Morales, A. G. Di Nuovo, M. Palesi, D. Patti. High Performance Computing for Embedded System Design: A Case Study. 11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 656-659, Sep. 3-5, 2008, Parma, Italy.

  50. R. Tornero, J. M. Orduna, M. Palesi, J. Duato. A Communication-Aware Topological Mapping Technique for NoCs. International Conference on Parallel and Distributed Computing, pp. 910-919, August 26-29th, 2008, Las Palmas de Gran Canaria, Spain.

  51. M. Palesi, G. Longo, S. Signorino, S. Kumar, R. Holsmark, V. Catania. Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. IEEE International Symposium on Networks-on-Chip, pp. 97-106, 7th-11th April 2008, Newcastle University, UK.

  52. G. Longo, S. Signorino, M. Palesi, S. Kumar, R. Holsmark, V. Catania.Bandwidth Aware Routing Algorithms for Networks-on-Chip. 2nd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip. Goteborg, Sweden, January 27, 2008.

  53. R. Tornero, J. M. Orduna, M. Palesi, J. Duato. A Communication-Aware Task Mapping Technique for NoCs. 2nd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip. Goteborg, Sweden, January 27, 2008.

  54. M. Palesi, S. Kumar, R. Holsmark, V. Catania. Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IEEE International Parallel and Distributed Processing Symposium, pp. 1-8, Long Beach, CA, March 2007.

  55. A. G. Di Nuovo, M. Palesi, V. Catania. Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. IEEE International Fuzzy Systems Conference. pp. 1-6, July 2007.

  56. G. Ascia, V. Catania, M. Palesi, D. Patti. Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. Fourth IEEE Workshop on Embedded Systems for Real Time Multimedia, pp. 79-84. Seoul, Korea, October 26-27, 2006.

  57. M. Palesi, R. Holsmark, S. Kumar, V. Catania. A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems. International Conference on Hardware-Software Codesign and System Synthesis, pp. 142-147. Seoul, Korea, October 22-25, 2006.

  58. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. Fuzzy Decision Making in Embedded System Design. International Conference on Hardware-Software Codesign and System Synthesis, Seoul, Korea, October 22-25, 2006.

  59. R. Holsmark, M. Palesi, S. Kumar. Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. DSD 2006, 9th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 696-703. Croatia, Sept 2006.

  60. M. Palesi, S. Kumar, R. Holsmark. A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. SAMOS VI Workshop: Embedded Computer Systems: Architectures, Modeling, and Simulation, pp. 373-384. Samos, Greece, July 17-20, 2006.

  61. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design. IC-SAMOS: Embedded Computer Systems: Architectures, Modeling, and Simulation. Samos, Greece, July 17-20, 2006.

  62. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. A Multi-objective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. IEEE Congress on Evolutionary Computation to be held in Sheraton Vancouver Wall Centre, Vancouver, BC, Canada, July 2006.

  63. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti.Fuzzy Simulation to Speedup Computer Design. In 4th Industrial Simulation Conference, pp. 285--289, Palermo, Italy, June 5--7 2006.

  64. G. Ascia, V. Catania, M. Palesi, D. Patti. A New Selection Policy for Adaptive Routing in Network on Chip. International Conference on Electronics, Hardware, Wireless and Optical Communications. Madrid, Spain, February 15-17, 2006.

  65. G. Ascia, V. Catania, M. Palesi. An Evolutionary Approach to Network-on-Chip Mapping Problem. IEEE Congress on Evolutionary Computation. Edinburgh, UK, September 2nd-5th, 2005.

  66. G. Ascia, V. Catania, M. Palesi, D. Patti. Exploring Design Space of VLIW Architectures. IEEE 16th International Conference on Application-specific Systems, Architectures and Processors. Samos, Greece, July 23-25, 2005.

  67. G. Ascia, V. Catania, M. Palesi, D. Patti. Hyperblock Formation: A Power/Energy Perspective for High Performance VLIW Architectures. IEEE International Symposium on Circuits and Systems 2005, Japan, May 21-26, 2005.

  68. G. Ascia, V. Catania, M. Palesi, D. Patti. A System-level Framework for Evaluating Area/Performance/Power Trade-offs of VLIW-based Embedded Systems. Asia and South Pacific Design Automation Conference 2005, Shanghai, Cina, Jan. 18-21, 2005.

  69. G. Ascia, V. Catania, M. Palesi, D. Patti. Power/Energy Perspective on Hyperblock Formation. International Conference on High Performance Computing. Bangalore, India, December 19-22, 2005.

  70. G. Ascia, V. Catania, M. Palesi. Multi-objective Mapping for Mesh-based NoC Architectures. In Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pages 182--187, Stockholm, Sweden, Sept. 8-10, 2004.

  71. G. Ascia, V. Catania, M. Palesi, and D. Patti. Multi-Objective Optimization of a Parameterized VLIW Architecture. In NASA/DoD Conference on Evolvable Hardware, Seattle, Washington, USA, Jun.24--26 2004.

  72. G. Ascia, V. Catania, M. Palesi, and A. Parlato. An evolutionary approach for reducing the switching activity in address buses. In Congress on Evolutionary Computation, Canberra, Australia, Dec.8--12 2003.

  73. G. Ascia, V. Catania, M. Palesi, and A. Parlato. A genetic approach to bus encoding. In IFIP International Conference on Very Large Scale Integration, Dec. 1--3 2003.

  74. G. Ascia, V. Catania, M. Palesi, and D. Patti. EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration. In First Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), Newport Beach, California, USA, Oct. 3--4 2003.

  75. G. Ascia, V. Catania, M. Palesi, and A. Parlato. An evolutionary approach for reducing the energy in address buses. In International Symposium on Information and Communication Technologies, Sept. 24--26 2003.

  76. G. Ascia, V. Catania, and M. Palesi. A genetic bus encoding technique for power optimization of embedded systems. In 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, Torino, Italy, Sept. 10--12 2003.

  77. G. Ascia, V. Catania, and M. Palesi. Tuning methodologies for parameterized systems design. In International Workshop on System-on-Chip for Real-Time Applications, Banff, Canada, July 6--7 2002.

  78. G. Ascia, V. Catania, and M. Palesi. Design space exploration methodologies for IP-based system-on-a-chip. In IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, May 26--29 2002.

  79. M. Palesi and T.Givargis. Multi-objective design space exploration using genetic algorithms. In Tenth International Symposium on Hardware/Software Codesign, Stanley Hotel, Estes Park, Colorado, USA, May 6--8 2002.

  80. G. Ascia, V. Catania, and M. Palesi. A framework for design space exploration of parameterized VLSI systems. In 7th Asia and South Pacific Design Automation Conference & 15th International Conference on VLSI Design, Bangalore, India, Jan. 7--11 2002.

  81. G. Ascia, V. Catania, and M. Palesi. A novel approach to design space exploration of parameterized SOCs. In IFIP International Conference on Very Large Scale Integration, The Global System on Chip Design & CAD Conference, 11th edition, pages 449--454, Montpellier, France, Dec. 2--5 2001.

  82. G. Ascia, V. Catania, and M. Palesi. Parameterized system design based on genetic algorithms. In 9th. International Symposium on Hardware/Software Co-Design, pages 177--182, Copenhagen, Denmark, Apr. 25--27 2001.