General Information

As the number of cores integrated into a System-on-Chip (SoC) increases, the role played by the interconnection system becomes more and more important. The International Technology Roadmap for Semiconductors depicts the on-chip communication issues as the limiting factors for performance and power consumption in current and next generation SoCs. Design in the era of ultra-deep submicron (UDSM) silicon is mainly dominated by issues concerning the communication infrastructure. While SoCs consisting of tens of cores were common in the last decade, common predictions foresee that the next generation of many-core SoCs will contain hundreds or thousands of cores. In the many-core era, as the number of cores residing on the same SoC increases significantly, the communication solutions also need to change drastically in order to support the new inter-core communication demands. It is nowadays widely recognized that Network-on-Chip (NoC) architectures represent the most viable solution to cope with scalability issues of future many-cores systems and to meet performance, power and reliability requirements which characterize future ambient intelligent applications.

The goal of the workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.

Areas of Interest

This workshop focuses on issues related to design, analysis and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:

Areas of Interest
NoC Performance Analysis	Dynamic On-chip Network Reconfiguration
Topology Selection and Synthesis for NoCs and MPSoCs	Modeling and Evaluation of On-chip Networks
Routing Algorithms and Router Micro-architectures	Design Space Exploration and Tradeoff Analysis
Guaranteed Throughput and Real Time On-chip Communication	On-chip Interconnection Network Simulators and Emulators
Mapping of Cores to NoCs	Validation, Debug and Test of NoCs and MpSoCs
Power and Energy Issues	3D NoC Architectures
Fault Tolerance and Reliability Issues	Emerging Technologies and New Design Paradigms
Memory Architectures for NoC	Industrial Case Studies of MpSoCs using the NoC Paradigm

Submission Guidelines

Both research and application-oriented papers are welcome. All papers should be submitted electronically by EasyChair. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author.

Papers must be formatted in accordance to the ACM style. ACM Word or LaTeX style templates are available here. In addition, Authors should apply ACM Computing Classification categories and terms. In order to be published, accepted papers must show a bibliographic strip containing the copyright statement (details).

Submissions must be limited to 6 pages. Papers deviating significantly from these paper size and formatting rules may be rejected without review. If the authors wish a blind review to be performed, then the author's name and affiliation should be omitted in the submitted paper. In case of any questions please contact the workshop organizers.

Important Dates

Final paper submission deadline	September 18, 2010
Author notification	October 18, 2010
Camera-ready version due	November 5, 2010
NoCArc Workshop	December 4, 2010

Committees

General Chairs

Maurizio Palesi		Shashi Kumar
University of Catania Italy		Jönköping University Sweden

Technical Program Chairs

Zhonghai Lu		Umit Y. Ogras
Royal Institute of Technology (KTH) Sweden		Strategic CAD Labs. Intel Corp. Hillsboro, OR

Technical Program Committee

• Federico Angiolini, iNoCs, Switzerland
• Giuseppe Ascia, University of Catania, Italy
• David Atienza, EPFL, Switzerland
• Davide Bertozzi, University of Ferrara, Italy
• Claas Cornelius, University of Rostock, Germany
• Giorgos Dimitrakopoulos, FORTH, Greece
• José Flich Cardo, Universidad Politécnica de Valencia, Spain
• Natalie Enright Jerger, University of Toronto, Canada
• Martti Forsell, VTT, Finland
• Manoj Singh Gaur, Malaviya National Institute of Technology, India
• Rickard Holsmark, Jönköping University, Sweden
• Yatin Hoskote, Intel Corp., USA
• Axel Jantsch, Royal Institute of Technology, Sweden
• Yuho Jin, University of Southern California, USA
• Shashi Kumar, Jönköping University, Sweden
• Erik Larsson, Linköping University, Sweden
• Zhonghai Lu, Royal Institute of Technology, Sweden
• Terrence Mak, Newcastle University, UK
• Radu Marculescu, Carnegie Mellon University, USA
• Johnny Öberg, Royal Institute of Technology, Sweden
• Umit Y. Ogras, Intel Corp., USA
• Juan Manuel Orduña Huertas, Universidad de Valencia, Spain
• Gianluca Palermo, Politecnico di Milano, Italy
• Maurizio Palesi, University of Catania, Italy
• Partha P. Pande, Washington State University, USA
• Sudeep Pasricha, Colorado State University, USA
• Carlo Pistritto, STMicroelectronics, Italy
• Davide Patti, University of Catania, Italy
• Alberto Scandurra, STMicroelectronics, Italy
• Christof Teuscher, Portland State University, USA
• Sriram R Vangal, Intel Corp., USA
• Yuan Xie, Pennsylvania State University, USA
• Mei Yang, University of Nevada, USA
• Vittorio Zaccaria, Politecnico di Milano, Italy

Past Editions

NoCArc 2009	2nd International Workshop on Network on Chip Architectures (NoCArc'09). Held in conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42), December 12, 2009, New York City, USA.
NoCArc 2008	1st International Workshop on Network on Chip Architectures (NoCArc'08). Held in conjunction with the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41), November 8, 2008, Lake Como, Italy.

Call for Papers

PDF flyer of the call-for-papers.

Proceedings

The proceedings of NoCArc 2010 will be published in the ACM Digital Library.

Special Issue

Authors of selected papers will be invited to submit an extended version of their work to contribute to a special issue of the ACM Transactions on Embedded Computing Systems (TECS).