First International Workshop on

Network on Chip Architectures

To be held in conjunction with the
41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41)
November 8th, 2008
Lake Como, Italy

NEW Proceedings are now available.


General Information

Single chip embedded systems are becoming increasingly complex and heterogeneous. Such Systems-on-Chip (SoCs) require seamless integration of numerous IP cores performing different functions and operating at different clock frequencies. Network-on-Chip (NoC) is generally viewed as the ultimate solution for the design of modular and scalable communication architectures, and provides inherent support to the integration of heterogeneous cores through the standardization of the network interfaces. This workshop is focused on issues related to design, analysis and testing of on-chip networks.

Areas of Interest

The topics of specific interest for the workshop include, but are not limited to:

The goal of the workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.

Submission Guidelines

Both research and application-oriented papers are welcome. All papers should be submitted electronically via the web. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author. Papers should be formatted in accordance with the following templates (standard double-column IEEE in A4 format):

Submissions must be limited to 6 pages. Papers deviating significantly from these paper size and formatting rules may be rejected without review. If the authors wish a blind review to be performed, then the author's name and affiliation should be omitted in the submitted paper. In case of any questions please contact the workshop organizers.

Important Dates

Submission deadline 24th August, 2008 12 midnight CET, 31st August 2008
Author notification 1st October, 2008
Camera-ready version due 10th October, 2008
NoCArc Workshop 8th November, 2008

Workshop Organizers

Program Committee

Final Program and Proceedings

13.30-14.20Opening Session
13.30-13.35Welcome from the Organizers
Maurizio Palesi and Shashi Kumar - University of Catania, Italy and Jönköping University, Sweden
13.35-14.15 Keynote talk: Managing Heterogeneity in Future NoCs
José Duato - UPV Valencia, Spain
14.20-15.00 Session I - Router Microarchitecture
Session Chair: Maurizio Palesi, University of Catania, Italy
14.20-14.40 Planar Adaptive Router Microarchitecture for Tree-Based Multicast Network-on-Chip
Faizal Arya Samman, Thomas Hollstein and Manfred Glesner - TU Darmstadt, Germany
14.40-15.00 DMesh: a Diagonally-Linked Mesh Network-on-Chip Architecture
Wen-Hsiang Hu, Seugn Eun Lee, and Nader Bagherzadeh - University of California, Irvine, USA
15.00-15.30Coffee Break
15.30-16.30 Session II - Performance Evaluation
Session Chair: Ahmed Hemani, Royal Institute of Technology, Sweden
15.30-15.50 A Generic Traffic Model for On-Chip Interconnection Networks
Jun Ho Bahn and Nader Bagherzadeh - Qualcomm Inc., USA and UC Irvine, USA
15.50-16.10 A System-C based Microarchitectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection Networks
Basavaraj Talwar and Bharadwaj Amrutur - ECE, Indian Institute of Science, Bangalore, India
16.10-16.30 Application Specific Buffer Allocation for Wormhole Routing Networks-on-Chip
Liwei Wang, Yang Cao, Xiaohui Li and Xiaohu Zhu - EIS, Wuhan University, China
16.40-17.40 Session III - Prospective Architectural Proposals
Session Chair: Shashi Kumar, Jönköping University, Sweden
16.40-17.00 Scalable CMOS-compatible photonic routing topologies for versatile networks on chip
Alberto Scandurra and Ian O'Connor - STMicrelectronics, Italy and Lyon Institute of Nanotechnology, France
17.00-17.20 Move Logic Not Data: A Conceptual Presentation
Ahmed Hemani and Muhammad Ali Shami - Royal Institute of Technology, KTH, Sweden
17.20-17.40 Hierarchical Agent Architecture for Scalable NoC Design with Online Monitoring Services
Alexander Wei Yin, Liang Guang, Pasi Liljeberg, Pekka Rantala, Ethiopia Nigussie, Jouni Isoaho and Hannu Tenhunen - University of Turku, Finland

 PDF version of the final program
 PDF version of the proceedings