Second International Workshop on

Network on Chip Architectures

To be held in conjunction with the
42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42)
December 12, 2009
New York City, USA

Proceedings and Special issue
The proceedings of NoCArc 2009 will be published in the ACM Digital Library and in the IEEE Xplore Authors of selected papers will be invited to submit an extended version of their work to contribute to a special issue of the Microprocessors and Microsystems Journal (MICPRO)


General Information

The continuous reduction in the time-to-market required by the telecommunications, multimedia and consumer electronics market makes full-custom design inappropriate and has led to the definition of design methodologies based on the reuse of Intellectual Properties (IPs, or cores). This has caused an increment in complexity and heterogeneity of single chip based embedded systems. In the many cores era, as the number of cores on a System-on-Chip (SoC) multiplies, on-chip communication solutions are evolving in order to support the new inter-core communication demands. Now-a-days it is recognized that traditional bus-based interconnect architectures have hit their scalability limit, and are no longer adequate for deep-sub-micron (DSM) technologies. The heterogeneity of the cores to be interconnected along with reliability and power-related issues and the need of introducing some kind of floorplan-awareness into each level of the design flow, represent additional issues which have to be addressed. Network-on-Chip (NoC) is generally viewed as the ultimate solution for the design of modular and scalable communication architectures, and provides inherent support to the integration of heterogeneous cores through the standardization of the network boundary. This workshop is focused on issues related to design, analysis and testing of on-chip networks.

Areas of Interest

The topics of specific interest for the workshop include, but are not limited to:

The goal of the workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.

Submission Guidelines

Both research and application-oriented papers are welcome. All papers should be submitted electronically by EasyChair. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author.

Papers must be formatted in accordance to the ACM style. ACM Word or LaTeX style templates are available here. In addition, Authors should apply ACM Computing Classification categories and terms. In order to be published, accepted papers must show a bibliographic strip containing the copyright statement (details).

Submissions must be limited to 6 pages. Papers deviating significantly from these paper size and formatting rules may be rejected without review. If the authors wish a blind review to be performed, then the author's name and affiliation should be omitted in the submitted paper. In case of any questions please contact the workshop organizers.

Important Dates

Submission deadline August 24, 2009 extended to September 4, 2009
Author notification October 1, 2009 October 6, 2009
Camera-ready version due October 10, 2009 October 16, 2009
NoCArc Workshop December 12, 2009

Workshop Organizers

Program Committee


08.45-09.45Opening Session
08.45-09.00Welcome from the Organizers slides
Maurizio Palesi and Shashi Kumar - University of Catania, Italy and Jönköping University, Sweden
09.00-09.45 Keynote talk: Toward a Science for Future NoC Design
Radu Marculescu - Carnegie Mellon University, USA
09.45-10.05Coffee Break
10.05-11.45 Session I - Router Architectures & Routing Algorithms
Session Chair: Radu Marculescu, Carnegie Mellon University, USA
10.05-10.30 Router Microarchitecture and Scalability of Ring Topology in On-Chip Networks
John Kim and Hanjoon Kim - KAIST Korea
10.30-10.55 Breaking Adaptive Multicast Deadlock By Virtual Channel Address/Data FIFO Decoupling
Ka-Ming Keung and Akhilesh Tyagi - Iowa State University, USA
10.55-11.20 Adaptive Router Architecture Based on Traffic Behavior Observability
Debora Matos, Caroline Concatto, Anelise Kologeski, Marcio Kreutz, Luigi Carro, Fernanda Kastensmidt and Altamiro Susin - UFRGS and UFRN Brazil
11.20-11.45 Path-Based, Randomized, Oblivious, Minimal (PROM) Routing
Myong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel Kinsy and Srinivas Devadas - Massachusetts Institute of Technology, USA
11.45-13.15Break for lunch
13.15-14.30 Session II - Design Methodologies & Mapping
Session Chair: José Flich Cardo, Universidad Politécnica de Valencia, Spain
13.15-13.40 Architecture Design Principles for the Integration of Synchronization Interfaces into Network-on-Chip Switches
Daniele Ludovici, Alessandro Strano, Davide Bertozzi - TUDelft, Netherlands and University of Ferrara, Italy
13.40-14.05 Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips
Anirban Dutta Choudhury, Gianluca Palermo, Cristina Silvano and Vittorio Zaccaria - ALaRI, Switzerland and Politecnico di Milano, Italy
14.05-14.30 The Era of Many-Modules SoC: Revisiting the NoC Mapping Problem
Isask'har Walter, Israel Cidon, Avinoam Kolodny and Daniel Sigalov - Technion, Israel Institute of Technology, Israel
14.30-14.45Coffee Break
14.45-16.00 Session III - Low Power Techniques & Performance Evaluation
Session Chair: Partha P. Pande, Washington State University, USA
14.45-15.10 A Performance Evaluation of 2D-Mesh, Ring, and Crossbar Interconnects for Chip Multi-Processors
Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Nils Gura and Wladek Olesinski - Universidad Politécnica de Valencia, Spain and Sun Microsystems, USA
15.10-15.35 Segment Gating for Static Energy Reduction in Networks-On-Chip
Kyle C. Hale, Boris Grot and Stephen W. Keckler - The University of Texas at Austin, USA
15.35-16.00 System-Level Exploration of Run-time Clusterization for Energy-efficient On-Chip Communication
Liang Guang, Ethiopia Nigussie and Hannu Tenhunen - Turku University, Finland
16.00-16.15Coffee Break
16.15-17.30 Session IV - Emerging Technologies & Novel Ideas
Session Chair: Christof Teuscher, Portland State University, USA
16.15-16.40 Hybrid Wireless Network on Chip: A New Paradigm in Multi-Core Design
Partha Pratim Pande, Amlan Ganguly, Kevin Chang, Christof Teuscher - Washington State University, USA and Portland State University, USA
16.40-17.05 Scalable Arbitration of Partitioned Bus Interconnection Networks in 3D-IC Systems
Kelli Ireland, Joseph Jezak, Steven Levitan and Donald Chiarulli - University of Pittsburgh, USA
17.05-17.30 Wire Cost and Communication Analysis of Self-Assembled Interconnect Models for Networks-on-Chip
Christof Teuscher, Neha Parashar, Mrugesh Mote, Nolan Hergert and Jonathan Aherne - Portland State University, USA and Carnegie Mellon University, USA