Maurizio Palesi, PhD

Associate Professor

Department of Electrical, Electronics and Computer Engineering
University of Catania, Italy
maurizio.palesi@dieei.unict.it


Index

Short Bio

My general research area is embedded systems design. An embedded system is almost any computing system other than a desktop computer or server. Examples include automobile cruise-control and fuel-injection, aircraft autopilots, telecommunication products, TV set-top boxes, network switches, VCR's, camcorders, robot controllers, medical devices, and audio/video encoders and decoders. I am interested mostly in single-chip implementations of complete embedded systems, known as system-on-a-chip, or SoC. The main research topics I am involved on are as follows:

My current research activity is mainly focused on on-chip interconnection systems (a.k.a., Networks-on-Chip - NoCs) with particular emphasis on application mapping and design methodologies for highly adaptive application specific routing algorithms. Since January 2007, I am member of the European Network of Excellence on High-Performance Embedded Architecture and Compilation (HiPEAC).

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Service

Editor of Special Issue

Conference/Workshop Organizer

Chair

Technical Program Committee Member

I serve as the Technical Program Committee Member for the following International Conferences and Workshops:

Editorial Board

Reviewer

I am actively involved as reviewer for the following international Journals: IEEE Transactions on Computers, IEEE Transactions on VLSI, IEEE Transactions on CAD, IEEE Transactions on Parallel and Distributed Systems, IEEE Computer Architecture Letters, Springer Design Automation for Embedded Systems, Elsevier Computers & Electrical Engineering, Elsevier Integration, the VLSI Journal, Elsevier Microelectronics Journal, IET Computers & Hindawi VLSI Design, International Journal of High Performance Systems Architecture, Digital Techniques, Computer Standards & Interfaces,

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Teaching

Ricevimento studenti previo appuntamento per email. 

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Seminars

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Publications

Most of the articles are copyright of IEEE, ACM, Springer (LNCS) or SCS. Please understand their copyright policy before reproducing these articles.

Books

  1. Maurizio Palesi and Masoud Daneshtalab. Routing Algorithms in Networks-on-Chip. Springer. ISBN 978-1-4614-8273-4.

Journal Papers

  1. A. Mineo, M. Palesi, G. Ascia, V. Catania. Exploiting Antenna Directivity in Wireless NoC Architectures. Microprocessors and Microsystems Elsevier. 2016. (doi:10.1016/j.micpro.2016.01.019)
  2. A. Mineo, M. Palesi, G. Ascia, P. P. Pande, V. Catania.On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling. Accepted for publication in Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016.
  3. M. Palesi, M. Collotta, M. Daneshtalab and P. Bose. Special Section on Energy Efficient Methods and Systems in the Emerging Cloud Computing Era. Journal of Computer and System Sciences. 82(2), March 2016.
  4. M. Tang, X. Lin, M. Palesi. Local Congestion Avoidance in Network-on-Chip. Accepted for publication in IEEE Transactions on Parallel and Distributed Systems. 2015.
  5. A. Mineo, M. Palesi, G. Ascia, V. Catania. Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures. Accepted for publication in IEEE Transactions on Very Large Scale Integration Systems, 2015
  6. N. Jafarzadeh, M. Palesi, S. Eskandari, S. Hessabi, A. Afzali-Kusha. Low Energy yet Reliable Data Communication Scheme for Networks on Chip. Accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015
  7. M. Palesi, M. Collotta, A. Mineo, V. Catania. An Efficient Radio Access Control Mechanism for Wireless Network-on-Chip Architectures. Journal of Low Power Electronics and Applications. 5(2) pp. 38-56, 2015.
  8. M. Palesi, D. Patti, G. Ascia, D. Panno, V. Catania. Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip. Journal of Computer Science, Science Publications, 11(3), pp. 552-566, 2015.
  9. M. Tang, X. Lin, M. Palesi. An Offline Method for Designing Adaptive Routing Based on Pressure Model. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 34(2), Feb. 2015, pp. 307-320.
  10. X. Wang, M. Yang, Y. Jiang, M. Daneshtalab, M. Palesi, T. Mak. On Self-tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation. ACM Transactions on Embedded Computing Systems. 13(2), Jan. 2014.
  11. N. Jafarzadeh, M. Palesi, A. Khademzadeh, A. Afzali-Kusha. Data Encoding Techniques for Reducing Energy Consumption in Networks on Chip. IEEE Transactions on Very Large Scale Integration (VLSI). 22(3), Mar. 2014.
  12. M. Daneshtalab, M. Palesi, J. Plosila, A. Hemani. Editorial of the Special issue on Many-core Embedded Systems. Elsevier Microprocessors and Microsystems, 38(6), Aug. 2014
  13. M. Tang, X. Lin, M. Palesi. Routing Pressure: A Channel-Related and Traffic-Aware Metric of Routing Algorithm. IEEE Transactions on Parallel and Distributed Systems. 26(3), July 2013.
  14. X. Wang, M. Yang, Y. Jiang, M. Palesi, P. Liu, T. Mak, N. Bagherzadeh.Efficient multicast schemes for 3-D Networks-on-Chip. Journal of Systems Architecture, 59(9), Oct. 2013, pp. 693–708.
  15. F. Shen, M. Palesi, M. Yang. Guest Editors Introduction to the Special Issue on Novel On-Chip Parallel Architectures and Software Support. Parallel Computing Journal, September 2013.
  16. T. Mak, M. Palesi, M. Daneshtalab. Editorial of the Special Issue on Emerging On-Chip Networks and Architectures. IET Computers & Digital Techniques, 2013. doi: 10.1049/iet-cdt.2013.0144
  17. X. Wang, P. Liu, M. Yang, M. Palesi, Y. Jiang, M. C. Huang. Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip. Springer, Journal of Computer Science and Technology, 28(1), pp. 54-71, January 2013.
  18. M. Palesi, R. Tornero, J. M. Orduna, D. Panno, V. Catania. Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip: A Multi-objective Evolutionary-based Approach. Journal of Universal Computer Science. 18(7), pp. 937-969.
  19. D. Patti, A. Spadaccini, M. Palesi, F. Fazzino, V. Catania. Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator. IEEE Transactions on Education. 55(3), pp. 406-411, Aug 2012.
  20. R. Al-Dujaily, T. Mak, F. Xia, A. Yakovlev, M. Palesi. Embedded Transitive Closure Network for Run-Time Deadlock Detection in Networks-on-Chip. IEEE Transactions on Parallel and Distributed Systems, 23(7), pp. 1205-1215, July 2012.
  21. F. Shen, M. Yang, M. Palesi: Guest Editors' Introduction to the Special Issue on Emerging Computing Architectures and Systems. Computers & Electrical Engineering 38(3): 722-723, 2012.
  22. M. Palesi, S. Kumar, R. Marculescu. Editorial of the Special Issue on Network on Chip Architectures and Design Methodologies. Elsevier Microprocessors and Microsystems Journal. Jan 2011.
  23. M. Palesi, G. Ascia, F. Fazzino, V. Catania. Data Encoding Schemes in Networks on Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(5), May 2011.
  24. M. Yang, Y. Jiang, P. Liu, M. Palesi. Editorial of the Special Issue on Power-Efficient, High Performance General Purpose and Application Specific Computing Architectures. International Journal of High Performance Systems Architecture. 2(3/4), 2010.
  25. G. Ascia, V. Catania, A. G. Di Nuovo, M. Palesi, D. Patti. Performance Evaluation of Efficient Multi-Objective Evolutionary Algorithms for Design Space Exploration of Embedded Computer Systems. Applied Soft Computing, 11(1), pp. 382-398, January 2011.
  26. M. Palesi, S. Kumar, V. Catania. Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(3), pp. 426-440, March 2010.
  27. M. Palesi, S. Kumar, V. Catania. Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms. Computers & Digital Techniques, IET, Vol. 3, No. 5. (11 August 2009), pp. 413-429.
  28. M. Palesi, R. Holsmark, S. Kumar, V. Catania. Application Specific Routing Algorithms for Networks on Chip. IEEE Transactions on Parallel and Distributed Systems, 20(3), pp. 316-330, March 2009.
  29. A. Mejia, M. Palesi, J. Flich, S. Kumar, P. Lopez, R. Holsmark and J. Duato.Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs IEEE Transactions on Very Large Scale Integration Systems, 17(3), pp. 356-369, March 2009.
  30. G. Ascia, V. Catania, M. Palesi, D. Patti. Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE Transactions on Computers, 57(6), pp. 809-820, June 2008.
  31. V. Catania, M. Palesi, D. Patti. Reducing Complexity of Multi-objective Design Space Exploration in VLIW-based Embedded Systems. ACM Transactions on Architecture and Code Optimization, 5(2), pp.11:1--11:33, Aug. 2008.
  32. V. Catania, M. Palesi, D. Patti. Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-objective Scenario. Journal of Circuits Systems and Computers, 16(5), pp. 819-846, Oct. 2007.
  33. R. Holsmark, M. Palesi, S. Kumar. Deadlock free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions. Journal of Systems Architecture, 54/3-4 (2008) pp. 427-440.
  34. D. Bertozzi, S. Kumar, M. Palesi. Networks-on-Chip: Emerging Research Topics and Novel Ideas. VLSI Design, vol. 2007, Article ID 26454, doi:10.1155/2007/26454.
  35. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. Efficient Design Space Exploration for Application Specific Systems-on-a-Chip. Journal of Systems Architecture, 53(10), pp. 733-750, Oct. 2007.
  36. G. Ascia, V. Catania, M. Palesi. A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. Journal of Universal Computer Science, 12(4):370--394, 2006.
  37. G. Ascia, V. Catania, M. Palesi. Mapping Cores on Network-on-Chip. International Journal of Computational Intelligence Research (IJCIR), ISSN            0972-9836      , 1(1-2):109--126, 2005.
  38. G. Ascia, V. Catania, M. Palesi, and A. Parlato. Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach. IEE Proceeding on Computers & Digital Techniques, 152(6):756--764, November 2005.
  39. G. Ascia, V. Catania, and M. Palesi. A Multi-objective Genetic Approach for System-level Exploration in Parameterized Systems-on-a-chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(4):635--645, April 2005.
  40. G. Ascia, V. Catania, and M. Palesi. A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms. IEEE Transactions on Evolutionary Computation, 8(2):329--346, August 2004.
  41. G. Ascia, V. Catania, M. Palesi, and D.Sarta. An instruction-level power analysis model with data dependency. VLSI Design, 12(2):245--273, 2001.

Chapter in Books

  1. M. Daneshtalab, M. Palesi. Basic Concepts on On-Chip Networks. In Routing Algorithms in Networks-on-Chip. Springer. 2013
  2. R. Al-Dujaily, T. Mak, F. Xia, A. Yakovlev, and M. Palesi. Run-Time Deadlock Detection. In Routing Algorithms in Networks-on-Chip. Springer. 2013
  3. M. Palesi, R. Holsmark, S. Kumar, and V. Catania. Application Specific Routing Algorithms for Low Power Network on Chip Design. Low Power Networks-on-Chip, Springer.
  4. G. Ascia, V. Catania, A. G. Di Nuovo, M. Palesi, and D. Patti. Computational Intelligence to Speed-Up Multi-Objective Design Space Exploration of Embedded SystemsMulti-Objective Optimization in Computational Intelligence: Theory and Practice. Lam Thu Bui (editor), Sameer Alam (editor), Chapter X, pp. 265-299, 2008.
  5. G. Ascia, V. Catania, and M. Palesi. An evolutionary approach for Pareto-optimal configurations in SOC platforms. In Kluwer Academic Pulishers, editor, SOC Design Methodologies, 2002.
  6. G. Ascia, V. Catania, and M. Palesi. Tuning methodologies for parameterized systems design. In Kluwer Academic Pulishers, editor, System on Chip for Realtime Systems, 2002.

Internal Reports

  1. G. Ascia, V. Catania, M. Palesi, D. Patti. A New Selection Strategy for On-Chip Networks. Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, Università di Catania, Italy, Spetember 2006.
  2. M. Palesi, R. Holsmark, S. Kumar, V. Catania. APSRA: A methodology for design of Application Specific Routing Algorithms for NoC Systems. Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, Università di Catania, Italy, April 2006.

Conference Papers

  1. V. Catania, A. Mineo, S. Monteleone, M. Palesi, D. Patti. Noxim: An Open, Extensible and Cycle-accurate Network on Chip Simulator. Accepted for IEEE International Conference on Application-specific Systems, Architectures and Processors 2015 takes place July 27-29, 2015 in Toronto, Canada.
  2. A. Mineo, M. S. Rusli, M. Palesi, G. Ascia, V. Catania, and M. N. Marsono. A Closed Loop Transmitting Power Self-Calibration Scheme for Energy Efficient WiNoC Architectures. Design Automation and Test in Europe (DATE 2015). Grenoble, France, March 9-12, 2015.
  3. M. Fattah, M. Palesi, P. Liljeberg, H. Tenhunen. SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems. Design Automation Conference (DAC 2014). DAC 2014. June 1-5, 2014.
  4. A. Mineo, M. Palesi, G. Ascia, V. Catania. An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs. Design Automation and Test in Europe (DATE 2014). Dresden, Germany, March 24-28, 2014.
  5. X. Wang, B. Zhao, T. Mak, M. Yang, Y. Jiang, M. Daneshtalab, M. Palesi. Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model. Design Automation and Test in Europe (DATE 2014). Dresden, Germany, March 24-28, 2014.
  6. D. Patti, M. Palesi, V. Catania. Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems. Modern Trends and Techniques in Computer Science, pp. 203-212, 2014.
  7. M. Masi, A. Mineo, M. Palesi, G. Ascia, V. Catania. Low Energy Mapping Techniques under Reliability and Bandwidth Constraints. 11th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2013), Zhangjiajie, China, November 13-15, 2013.
  8. A. Mineo, M. Palesi, G. Ascia, V. Catania. Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. EUROMICRO DSD/SEAA 2013, Santander, Spain, September 4-6, 2013.
  9. G. Ascia, M. Palesi, V. Catania. An adaptive output selection function based on a fuzzy rule base system for Network on Chip. EUROMICRO DSD/SEAA 2013, Santander, Spain, September 4-6, 2013.
  10. A. Mineo, M. Palesi, G. Ascia, V. Catania. NoC Links Energy Reduction through Link Voltage Scaling. 13th International Conference on Embedded Computer Systems: Architectures, Modeling, and Siimulation (SAMOS XIII), Samos, Greece, July 15–18, 2013.
  11. X. Wang, T. Mak, M. Yang, Y. Jiang, M. Daneshtalab, M. Palesi. On Self-Tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation. To be presented at 7th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), April 2013, Tempe, Arizona.
  12. M. Ebrahimi, M. Daneshtalab, F. Farahnakian, P. Liljeberg, J. Plosila, M. Palesi, and H. Tenhunen, "HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks," in Proceedings of 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 19-26, May. 2012, Denmark.
  13. D. Patti, A. Spadaccini, M. Palesi, F. Fazzino, and V. Catania. Improving the Teaching Effectiveness in an Introductory Computer Architecture Course. International Conference on Computational Intelligence and Software Engineering, 2011.
  14. X. Wang, M. Palesi, M. Yang, Y. Jiang, M. C. Huang, P. Liu. Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip. Lecture Notes in Computer Science, vol. 6985, Network and Parallel Computing Conference, 2011.
  15. X. Wang, M. Palesi, M. Yang, Y. Jiang, M. C. Huang, P. Liu. Low Latency and Energy Efficient Multicasting Schemes for 3D NoC-based SoCs. VLSI System on Chip. October 2011, Kowloon, Hong Kong, China.
  16. D. Salemi, M. Palesi, V. Catania. Power-Aware Selection Policy for Networks on Chip. 6th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS'11). 6-8 APril 2011, Athens, Greece.
  17. Al-Dujaily, T. Mak, F. Xia, A. Yakovlev, M. Palesi. Run-time Deadlock Detection in Networks-on-Chip using Coupled Transitive Closure Networks. Design Automation and Test in Europe (DATE 2011). 14-18 March 2011, Grenoble, France. Best Paper Award
  18. R. Holsmark, S. Kumar, M. Palesi. A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms. 4th Workshop on Highly Parallel Processing on a Chip (HPPC 2010), August 31, 2010, Ischia - Naples, Italy. [To appear]
  19. M. Palesi, R. Holsmark, X. Wang, S. Kumar, M. Yang, Y. Jiang, V. Catania. A Novel Mechanism to Guarantee In-Order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. 13th Euromicro Conference On Digital System Design Architectures, Methods and Tools Lille, France, 1-3 September, 2010. [To appear]
  20. M. Palesi, R. Holsmark, X. Wang, S. Kumar, M. Yang, Y. Jiang, V. Catania. An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip. 4th Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, held in conjunction with the: 5th International Conference on High Performance Embedded Architectures and Compilers, Pisa, Italy, January 24, 2010.
  21. M. Palesi and S. Kumar. Message from the Chairs. 2nd International Workshop on Network on Chip Architectures, held in conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Dec 12, 2009, New York, New York, USA.
  22. G. Ascia, V. Catania, F. Fazzino, M. Palesi. An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip. IEEE International Conference on Computer Engineering and Systems, 14-16 Dec 2009, Cairo, Egypt.
  23. V. Catania, G. De Francisci Morales, A. G. Di Nuovo, M. Palesi, D. Patti. An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures. 12th Euromicro Conference on Digital System Design, 27-29 Aug 2009, Patras, Greece.
  24. M. Palesi, F. Fazzino, G. Ascia, V. Catania. Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. 12th Euromicro Conference on Digital System Design, 27-29 Aug 2009, Patras, Greece.
  25. R. Tornero, V. Sterrantino, M. Palesi, J. M. Orduna. A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip. IEEE/ACM International Symposium on Parallel & Distributed Processing, 25-28 May, 2009, Rome, Italy.
  26. R. Holsmark, M. Palesi, S. Kumar, A. Mejia. HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip. 3rd ACM/IEEE International Symposium on Networks on Chip. May 10-13, 2009, San Diego, CA
  27. D. Frazzetta, G. Dimartino, M. Palesi, S. Kumar, V. Catania. Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. 11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 18-25, Sep. 3-5, 2008, Parma, Italy.
  28. V. Catania, G. De Francisci Morales, A. G. Di Nuovo, M. Palesi, D. Patti. High Performance Computing for Embedded System Design: A Case Study. 11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 656-659, Sep. 3-5, 2008, Parma, Italy.
  29. R. Tornero, J. M. Orduna, M. Palesi, J. Duato. A Communication-Aware Topological Mapping Technique for NoCs. International Conference on Parallel and Distributed Computing, pp. 910-919, August 26-29th, 2008, Las Palmas de Gran Canaria, Spain.
  30. M. Palesi, G. Longo, S. Signorino, S. Kumar, R. Holsmark, V. Catania. Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. IEEE International Symposium on Networks-on-Chip, pp. 97-106, 7th-11th April 2008, Newcastle University, UK.
  31. G. Longo, S. Signorino, M. Palesi, S. Kumar, R. Holsmark, V. Catania.Bandwidth Aware Routing Algorithms for Networks-on-Chip. 2nd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip. Goteborg, Sweden, January 27, 2008.
  32. R. Tornero, J. M. Orduna, M. Palesi, J. Duato. A Communication-Aware Task Mapping Technique for NoCs. 2nd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip. Goteborg, Sweden, January 27, 2008.
  33. M. Palesi, S. Kumar, R. Holsmark, V. Catania. Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IEEE International Parallel and Distributed Processing Symposium, pp. 1-8, Long Beach, CA, March 2007.
  34. A. G. Di Nuovo, M. Palesi, V. Catania. Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. IEEE International Fuzzy Systems Conference. pp. 1-6, July 2007.
  35. G. Ascia, V. Catania, M. Palesi, D. Patti. Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. Fourth IEEE Workshop on Embedded Systems for Real Time Multimedia, pp. 79-84. Seoul, Korea, October 26-27, 2006.
  36. M. Palesi, R. Holsmark, S. Kumar, V. Catania. A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems. International Conference on Hardware-Software Codesign and System Synthesis, pp. 142-147. Seoul, Korea, October 22-25, 2006.
  37. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. Fuzzy Decision Making in Embedded System Design. International Conference on Hardware-Software Codesign and System Synthesis, Seoul, Korea, October 22-25, 2006.
  38. R. Holsmark, M. Palesi, S. Kumar. Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. DSD 2006, 9th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 696-703. Croatia, Sept 2006.
  39. M. Palesi, S. Kumar, R. Holsmark. A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. SAMOS VI Workshop: Embedded Computer Systems: Architectures, Modeling, and Simulation, pp. 373-384. Samos, Greece, July 17-20, 2006.
  40. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design. IC-SAMOS: Embedded Computer Systems: Architectures, Modeling, and Simulation. Samos, Greece, July 17-20, 2006.
  41. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. A Multi-objective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. IEEE Congress on Evolutionary Computation to be held in Sheraton Vancouver Wall Centre, Vancouver, BC, Canada, July 2006.
  42. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti.Fuzzy Simulation to Speedup Computer Design. In 4th Industrial Simulation Conference, pp. 285--289, Palermo, Italy, June 5--7 2006.
  43. G. Ascia, V. Catania, M. Palesi, D. Patti. A New Selection Policy for Adaptive Routing in Network on Chip. International Conference on Electronics, Hardware, Wireless and Optical Communications. Madrid, Spain, February 15-17, 2006.
  44. G. Ascia, V. Catania, M. Palesi. An Evolutionary Approach to Network-on-Chip Mapping Problem. IEEE Congress on Evolutionary Computation. Edinburgh, UK, September 2nd-5th, 2005.
  45. G. Ascia, V. Catania, M. Palesi, D. Patti. Exploring Design Space of VLIW Architectures. IEEE 16th International Conference on Application-specific Systems, Architectures and Processors. Samos, Greece, July 23-25, 2005.
  46. G. Ascia, V. Catania, M. Palesi, D. Patti. Hyperblock Formation: A Power/Energy Perspective for High Performance VLIW Architectures. IEEE International Symposium on Circuits and Systems 2005, Japan, May 21-26, 2005.
  47. G. Ascia, V. Catania, M. Palesi, D. Patti. A System-level Framework for Evaluating Area/Performance/Power Trade-offs of VLIW-based Embedded Systems. Asia and South Pacific Design Automation Conference 2005, Shanghai, Cina, Jan. 18-21, 2005.
  48. G. Ascia, V. Catania, M. Palesi, D. Patti. Power/Energy Perspective on Hyperblock Formation. International Conference on High Performance Computing. Bangalore, India, December 19-22, 2005.
  49. G. Ascia, V. Catania, M. Palesi. Multi-objective Mapping for Mesh-based NoC Architectures. In Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pages 182--187, Stockholm, Sweden, Sept. 8-10, 2004.
  50. G. Ascia, V. Catania, M. Palesi, and D. Patti. Multi-Objective Optimization of a Parameterized VLIW Architecture. In NASA/DoD Conference on Evolvable Hardware, Seattle, Washington, USA, Jun.24--26 2004.
  51. G. Ascia, V. Catania, M. Palesi, and A. Parlato. An evolutionary approach for reducing the switching activity in address buses. In Congress on Evolutionary Computation, Canberra, Australia, Dec.8--12 2003.
  52. G. Ascia, V. Catania, M. Palesi, and A. Parlato. A genetic approach to bus encoding. In IFIP International Conference on Very Large Scale Integration, Dec. 1--3 2003.
  53. G. Ascia, V. Catania, M. Palesi, and D. Patti. EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration. In First Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), Newport Beach, California, USA, Oct. 3--4 2003.
  54. G. Ascia, V. Catania, M. Palesi, and A. Parlato. An evolutionary approach for reducing the energy in address buses. In International Symposium on Information and Communication Technologies, Sept. 24--26 2003.
  55. G. Ascia, V. Catania, and M. Palesi. A genetic bus encoding technique for power optimization of embedded systems. In 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, Torino, Italy, Sept. 10--12 2003.
  56. G. Ascia, V. Catania, and M. Palesi. Tuning methodologies for parameterized systems design. In International Workshop on System-on-Chip for Real-Time Applications, Banff, Canada, July 6--7 2002.
  57. G. Ascia, V. Catania, and M. Palesi. Design space exploration methodologies for IP-based system-on-a-chip. In IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, May 26--29 2002.
  58. M. Palesi and T.Givargis. Multi-objective design space exploration using genetic algorithms. In Tenth International Symposium on Hardware/Software Codesign, Stanley Hotel, Estes Park, Colorado, USA, May 6--8 2002.
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