Maurizio Palesi, PhD
University of Catania
Department of Computer Science and Telecommunications Engineering (DIIT)
6, Viale Andrea Doria
95125 Catania, Italy
Phone: +39 095 738 2385, Fax: +39 095 7382397
Email: mpalesi [at] diit.unict.it

NEW: Special Issue on Network-on-Chip Architectures and Design Methodologies in Elsevier Microprocessors and Microsystems - Embedded Hardware Design (Editors: Maurizio Palesi, Shashi Kumar, Radu Marculescu)

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Short Bio

My general research area is embedded systems design. An embedded system is almost any computing system other than a desktop computer or server. Examples include automobile cruise-control and fuel-injection, aircraft autopilots, telecommunication products, TV set-top boxes, network switches, VCR's, camcorders, robot controllers, medical devices, and audio/video encoders and decoders. I am interested mostly in single-chip implementations of complete embedded systems, known as system-on-a-chip, or SoC. The main research topics I am involved on are as follows:

My current research activity is mainly focused on on-chip interconnection systems (a.k.a., Networks-on-Chip - NoCs) with particular emphasis on application mapping and design methodologies for highly adaptive application specific routing algorithms. Since January 2007, I am member of the European Network of Excellence on High-Performance Embedded Architecture and Compilation (HiPEAC). Since May 2007, I serve on the Editorial Board of VLSI Design as Associate Editor.

I serve as the Technical Program Committee Member for the following International Conferences:

I am actively involved as reviewer for the following international Journals: IEEE Transactions on Computers, IEEE Transactions on VLSI, IEEE Transactions on CAD, IEEE Transactions on Parallel and Distributed Systems, IEEE Computer Architecture Letters, Springer Design Automation for Embedded Systems, Elsevier Computers & Electrical Engineering, Elsevier Integration, the VLSI Journal, Elsevier Microelectronics Journal, IET Computers & Hindawi VLSI Design, International Journal of High Performance Systems Architecture, Digital Techniques, Computer Standards & Interfaces,

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Special Issues and Conferences

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Research Team and Collaborations

People involved in my research activity in Catania are as follows.

Since September 2005 I have closely cooperated with Prof. Shashi Kumar of the Department of Electronics and Computer Engineering, School of Engineering, Jönköping University, Sweden. The joint research activity is mainly focused on several aspects of Network-on-Chip (NoC) architectures with particular emphasis on the design of application-specific deadlock-free routing algorithms for NoC platforms. Since January 2007, he has cooperated with Prof. José Flich of the Universidad Politecnica de Valencia DISCA (Spain) and Prof. Juan Manuel Orduna of Universidad de Valencia (Spain).

The joint research activity is supported by the European Network of Excellence on High-Performance Embedded Architecture and Compilation (HiPEAC) by a cluster project entitled Research on high performance interconnection networks for embedded applications.

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Teaching

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Seminars

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Publications

Most of the articles are copyright of IEEE, ACM, Springer (LNCS) or SCS. Please understand their copyright policy before reproducing these articles.

Journal Papers

  1. G. Ascia, V. Catania, A. G. Di Nuovo, M. Palesi, D. Patti. Performance Evaluation of Efficient Multi-Objective Evolutionary Algorithms for Design Space Exploration of Embedded Computer Systems. Accepted for publication in Applied Soft Computing.
  2. M. Palesi, S. Kumar, V. Catania. Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip. Accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
  3. M. Palesi, S. Kumar, V. Catania. Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms. Computers & Digital Techniques, IET, Vol. 3, No. 5. (11 August 2009), pp. 413-429.
  4. M. Palesi, R. Holsmark, S. Kumar, V. Catania. Application Specific Routing Algorithms for Networks on Chip. IEEE Transactions on Parallel and Distributed Systems, 20(3), pp. 316-330, March 2009.
  5. A. Mejia, M. Palesi, J. Flich, S. Kumar, P. Lopez, R. Holsmark and J. Duato. Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs IEEE Transactions on on Very Large Scale Integration Systems, 17(3), pp. 356-369, March 2009.
  6. G. Ascia, V. Catania, M. Palesi, D. Patti. Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE Transactions on Computers, 57(6), pp. 809-820, June 2008.
  7. V. Catania, M. Palesi, D. Patti. Reducing Complexity of Multi-objective Design Space Exploration in VLIW-based Embedded Systems. ACM Transactions on Architecture and Code Optimization, 5(2), pp.11:1--11:33, Aug. 2008.
  8. V. Catania, M. Palesi, D. Patti. Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-objective Scenario. Journal of Circuits Systems and Computers, 16(5), pp. 819-846, Oct. 2007.
  9. R. Holsmark, M. Palesi, S. Kumar. Deadlock free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions. Journal of Systems Architecture, 54/3-4 (2008) pp. 427-440.
  10. D. Bertozzi, S. Kumar, M. Palesi. Networks-on-Chip: Emerging Research Topics and Novel Ideas. VLSI Design, vol. 2007, Article ID 26454, doi:10.1155/2007/26454.
  11. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. Efficient Design Space Exploration for Application Specific Systems-on-a-Chip. Journal of Systems Architecture, 53(10), pp. 733-750, Oct. 2007.
  12. G. Ascia, V. Catania, M. Palesi. A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. Journal of Universal Computer Science, 12(4):370--394, 2006.
  13. G. Ascia, V. Catania, M. Palesi. Mapping Cores on Network-on-Chip. International Journal of Computational Intelligence Research (IJCIR), ISSN 0972-9836, 1(1-2):109--126, 2005.
  14. G. Ascia, V. Catania, M. Palesi, and A. Parlato. Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach. IEE Proceeding on Computers & Digital Techniques, 152(6):756--764, November 2005.
  15. G. Ascia, V. Catania, and M. Palesi. A Multi-objective Genetic Approach for System-level Exploration in Parameterized Systems-on-a-chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(4):635--645, April 2005.
  16. G. Ascia, V. Catania, and M. Palesi. A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms. IEEE Transactions on Evolutionary Computation, 8(2):329--346, August 2004.
  17. G. Ascia, V. Catania, M. Palesi, and D.Sarta. An instruction-level power analysis model with data dependency. VLSI Design, 12(2):245--273, 2001.

Chapter in Books

  1. G. Ascia, V. Catania, A. G. Di Nuovo, M. Palesi, and D. Patti. Computational Intelligence to Speed-Up Multi-Objective Design Space Exploration of Embedded Systems. Multi-Objective Optimization in Computational Intelligence: Theory and Practice. Lam Thu Bui (editor), Sameer Alam (editor), Chapter X, pp. 265-299, 2008.
  2. G. Ascia, V. Catania, and M. Palesi. An evolutionary approach for Pareto-optimal configurations in SOC platforms. In Kluwer Academic Pulishers, editor, SOC Design Methodologies, 2002.
  3. G. Ascia, V. Catania, and M. Palesi. Tuning methodologies for parameterized systems design. In Kluwer Academic Pulishers, editor, System on Chip for Realtime Systems, 2002.

Internal Reports

  1. G. Ascia, V. Catania, M. Palesi, D. Patti. A New Selection Strategy for On-Chip Networks. Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, Università di Catania, Italy, Spetember 2006.
  2. M. Palesi, R. Holsmark, S. Kumar, V. Catania. APSRA: A methodology for design of Application Specific Routing Algorithms for NoC Systems. Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, Università di Catania, Italy, April 2006.

Conference Papers

  1. M. Palesi, R. Holsmark, X. Wang, S. Kumar, M. Yang, Y. Jiang, V. Catania. An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip. 4th Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, held in conjunction with the: 5th International Conference on High Performance Embedded Architectures and Compilers, Pisa, Italy, January 24, 2010.
  2. M. Palesi and S. Kumar. Message from the Chairs. 2nd International Workshop on Network on Chip Architectures, held in conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Dec 12, 2009, New York, New York, USA.
  3. G. Ascia, V. Catania, F. Fazzino, M. Palesi. An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip. IEEE International Conference on Computer Engineering and Systems, 14-16 Dec 2009, Cairo, Egypt.
  4. V. Catania, G. De Francisci Morales, A. G. Di Nuovo, M. Palesi, D. Patti. An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures. 12th Euromicro Conference on Digital System Design, 27-29 Aug 2009, Patras, Greece.
  5. M. Palesi, F. Fazzino, G. Ascia, V. Catania. Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. 12th Euromicro Conference on Digital System Design, 27-29 Aug 2009, Patras, Greece.
  6. R. Tornero, V. Sterrantino, M. Palesi, J. M. Orduna. A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip. IEEE/ACM International Symposium on Parallel & Distributed Processing, 25-28 May, 2009, Rome, Italy.
  7. R. Holsmark, M. Palesi, S. Kumar, A. Mejia. HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip. 3rd ACM/IEEE International Symposium on Networks on Chip. May 10-13, 2009, San Diego, CA
  8. D. Frazzetta, G. Dimartino, M. Palesi, S. Kumar, V. Catania. Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. 11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 18-25, Sep. 3-5, 2008, Parma, Italy.
  9. V. Catania, G. De Francisci Morales, A. G. Di Nuovo, M. Palesi, D. Patti. High Performance Computing for Embedded System Design: A Case Study. 11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 656-659, Sep. 3-5, 2008, Parma, Italy.
  10. R. Tornero, J. M. Orduna, M. Palesi, J. Duato. A Communication-Aware Topological Mapping Technique for NoCs. International Conference on Parallel and Distributed Computing, pp. 910-919, August 26-29th, 2008, Las Palmas de Gran Canaria, Spain.
  11. M. Palesi, G. Longo, S. Signorino, S. Kumar, R. Holsmark, V. Catania. Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. IEEE International Symposium on Networks-on-Chip, pp. 97-106, 7th-11th April 2008, Newcastle University, UK.
  12. G. Longo, S. Signorino, M. Palesi, S. Kumar, R. Holsmark, V. Catania. Bandwidth Aware Routing Algorithms for Networks-on-Chip. 2nd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip. Goteborg, Sweden, January 27, 2008.
  13. R. Tornero, J. M. Orduna, M. Palesi, J. Duato. A Communication-Aware Task Mapping Technique for NoCs. 2nd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip. Goteborg, Sweden, January 27, 2008.
  14. M. Palesi, S. Kumar, R. Holsmark, V. Catania. Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IEEE International Parallel and Distributed Processing Symposium, pp. 1-8, Long Beach, CA, March 2007.
  15. A. G. Di Nuovo, M. Palesi, V. Catania. Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. IEEE International Fuzzy Systems Conference. pp. 1-6, July 2007.
  16. G. Ascia, V. Catania, M. Palesi, D. Patti. Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. Fourth IEEE Workshop on Embedded Systems for Real Time Multimedia, pp. 79-84. Seoul, Korea, October 26-27, 2006.
  17. M. Palesi, R. Holsmark, S. Kumar, V. Catania. A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems. International Conference on Hardware-Software Codesign and System Synthesis, pp. 142-147. Seoul, Korea, October 22-25, 2006.
  18. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. Fuzzy Decision Making in Embedded System Design. International Conference on Hardware-Software Codesign and System Synthesis, Seoul, Korea, October 22-25, 2006.
  19. R. Holsmark, M. Palesi, S. Kumar. Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. DSD 2006, 9th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, pp. 696-703. Croatia, Sept 2006.
  20. M. Palesi, S. Kumar, R. Holsmark. A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. SAMOS VI Workshop: Embedded Computer Systems: Architectures, Modeling, and Simulation, pp. 373-384. Samos, Greece, July 17-20, 2006.
  21. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design. IC-SAMOS: Embedded Computer Systems: Architectures, Modeling, and Simulation. Samos, Greece, July 17-20, 2006.
  22. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti. A Multi-objective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. IEEE Congress on Evolutionary Computation to be held in Sheraton Vancouver Wall Centre, Vancouver, BC, Canada, July 2006.
  23. G. Ascia, V. Catania, A. Di Nuovo, M. Palesi, D. Patti.Fuzzy Simulation to Speedup Computer Design. In 4th Industrial Simulation Conference, pp. 285--289, Palermo, Italy, June 5--7 2006.
  24. G. Ascia, V. Catania, M. Palesi, D. Patti. A New Selection Policy for Adaptive Routing in Network on Chip. International Conference on Electronics, Hardware, Wireless and Optical Communications. Madrid, Spain, February 15-17, 2006.
  25. G. Ascia, V. Catania, M. Palesi. An Evolutionary Approach to Network-on-Chip Mapping Problem. IEEE Congress on Evolutionary Computation. Edinburgh, UK, September 2nd-5th, 2005.
  26. G. Ascia, V. Catania, M. Palesi, D. Patti. Exploring Design Space of VLIW Architectures. IEEE 16th International Conference on Application-specific Systems, Architectures and Processors. Samos, Greece, July 23-25, 2005.
  27. G. Ascia, V. Catania, M. Palesi, D. Patti. Hyperblock Formation: A Power/Energy Perspective for High Performance VLIW Architectures. IEEE International Symposium on Circuits and Systems 2005, Japan, May 21-26, 2005.
  28. G. Ascia, V. Catania, M. Palesi, D. Patti. A System-level Framework for Evaluating Area/Performance/Power Trade-offs of VLIW-based Embedded Systems. Asia and South Pacific Design Automation Conference 2005, Shanghai, Cina, Jan. 18-21, 2005.
  29. G. Ascia, V. Catania, M. Palesi, D. Patti. Power/Energy Perspective on Hyperblock Formation. International Conference on High Performance Computing. Bangalore, India, December 19-22, 2005.
  30. G. Ascia, V. Catania, M. Palesi. Multi-objective Mapping for Mesh-based NoC Architectures. In Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pages 182--187, Stockholm, Sweden, Sept. 8-10, 2004.
  31. G. Ascia, V. Catania, M. Palesi, and D. Patti. Multi-Objective Optimization of a Parameterized VLIW Architecture. In NASA/DoD Conference on Evolvable Hardware, Seattle, Washington, USA, Jun.24--26 2004.
  32. G. Ascia, V. Catania, M. Palesi, and A. Parlato. An evolutionary approach for reducing the switching activity in address buses. In Congress on Evolutionary Computation, Canberra, Australia, Dec.8--12 2003.
  33. G. Ascia, V. Catania, M. Palesi, and A. Parlato. A genetic approach to bus encoding. In IFIP International Conference on Very Large Scale Integration, Dec. 1--3 2003.
  34. G. Ascia, V. Catania, M. Palesi, and D. Patti. EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration. In First Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), Newport Beach, California, USA, Oct. 3--4 2003.
  35. G. Ascia, V. Catania, M. Palesi, and A. Parlato. An evolutionary approach for reducing the energy in address buses. In International Symposium on Information and Communication Technologies, Sept. 24--26 2003.
  36. G. Ascia, V. Catania, and M. Palesi. A genetic bus encoding technique for power optimization of embedded systems. In 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, Torino, Italy, Sept. 10--12 2003.
  37. G. Ascia, V. Catania, and M. Palesi. Tuning methodologies for parameterized systems design. In International Workshop on System-on-Chip for Real-Time Applications, Banff, Canada, July 6--7 2002.
  38. G. Ascia, V. Catania, and M. Palesi. Design space exploration methodologies for IP-based system-on-a-chip. In IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, May 26--29 2002.
  39. M. Palesi and T.Givargis. Multi-objective design space exploration using genetic algorithms. In Tenth International Symposium on Hardware/Software Codesign, Stanley Hotel, Estes Park, Colorado, USA, May 6--8 2002.
  40. G. Ascia, V. Catania, and M. Palesi. A framework for design space exploration of parameterized VLSI systems. In 7th Asia and South Pacific Design Automation Conference & 15th International Conference on VLSI Design, Bangalore, India, Jan. 7--11 2002.
  41. G. Ascia, V. Catania, and M. Palesi. A novel approach to design space exploration of parameterized SOCs. In IFIP International Conference on Very Large Scale Integration, The Global System on Chip Design & CAD Conference, 11th edition, pages 449--454, Montpellier, France, Dec. 2--5 2001.
  42. G. Ascia, V. Catania, and M. Palesi. Parameterized system design based on genetic algorithms. In 9th. International Symposium on Hardware/Software Co-Design, pages 177--182, Copenhagen, Denmark, Apr. 25--27 2001.
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Research References

Reference Description
CiteSeer NEC Research Institute CiteSeer
SIGDA Proceedings SIGDA Proceedings Archive
ISLPED Proceedings ISLPED Proceedings Archive
EE Times The industry source for engineers
EE Design Resource for design tools and methodologies
IEEE Explorer IEEE Digital Library
TC IEEE Transactions on Computers
TVLSI IEEE Transactions on Very Large Scale Integration Systems
TCAD IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TECS ACM Transactions in Embedded Computing Systems
TODAES ACM Transactions on Design Automation of Electronic Systems
D&T IEEE Design and Test
Computer IEEE Computer
VLSI Design VLSI Design
DAES Design Automation for Embedded Systems
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Miscellaneous

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Santy Giuffrida My Mum's homepage
Web Mail UniCT Web Mail
BDS 24 Banco di Sicilia, BDS 24ore service
Conto Arancio ING Direct Conto Arancio
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IP-Atlas IP-Atlas demo
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Televideo RAI Televideo RAI (solo testo)
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Cartoonizer Funky ways to express yourself
Time Zone Converter To find out the time anywhere in the world
Dartbase DARTS! Darts thrower
SportyPal Running and cycling monitoring
Upvise contacts Contacts Sync
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(C) 2004-2008 by Maurizio Palesi