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Program
| 09.15-09.30 | Opening | Maurizio Palesi, Terrence Mak, and Masoud Daneshtalab |
| 09.30-10.30 | Keynote: Millimeter (mm)-Wave Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges | Partha Pratim Pande, Washington State University |
| 10.30-11.00 | Coffee break | |
| 11.00-12.30 | Session I - Routing Algorithms and Topologies | |
|---|---|---|
| Chair: Partha Pande, Washington State University | ||
| 11.00 | LEF: Long Edge First Routing for Two-Dimensional Mesh Network on Chip | Ryosuke Sasakawa and Kenji Kise |
| 11.25 | User satisfaction aware routing decisions in NOC | Swamy Ponpandi and Akhilesh Tyagi |
| 11.50 | On Multicast for Dynamic and Irregular On-Chip Networks Using Dynamic Programming Method | Wen Zong, Xiaohang Wang and Terrence Mak |
| 12.15 | [short] Towards Optimal Adaptive Routing in 3D NoC with Limited Vertical Bandwidth | Gunhee Lee, Jinho Lee and Kiyoung Choi |
| 12.30-13.30 | Lunch | |
| 13.30-15.00 | Session II - Network Design | |
| Chair: Nader Bagherzadeh, University of California Irvine | ||
| 13.30 | On Heterogeneous Network-on-Chip Design Based on Constraint Programming | Ayhan Demiriz and Nader Bagherzadeh |
| 13.55 | Design Space Exploration for Streaming Applications on Multiprocessors with Guaranteed Service NoC | Usman Mazhar Mirza, Flavius Gruian and Krzysztof Kuchcinski |
| 14.20 | Costs and Benefits of Flexibility in Spatial Division Circuit Switched Networks-on-Chip | Ahsen Ejaz and Axel Jantsch |
| 14.45 | [short] Empirical and Theoretical Lower Bounds on Energy Consumption for Networks on Chip | George Bezerra, Stephanie Forrest and Dorian Arnold |
| 15.00-15.30 | Coffee break | |
| 15.30-16.35 | Session III - Emerging Technologies and Modeling | |
| Chair: Maurizio Palesi, Kore University, Italy | ||
| 15.30 | Exploiting Emerging Technologies for Nanoscale Photonic Networks-on-Chip | Jun Pang, Christopher Dwyer and Alvin R. Lebeck |
| 15.55 | A First Effort for a Distributed Segment-based Approach on Self-Assembled | Vincenzo Catania, Andrea Mineo, Salvatore Monteleone and Davide Patti |
| 16.20 | [short] Modeling and Analyzing Timing Faults in Transaction Level SystemC Programs | Reza Hajisheykhi, Ali Ebnenasir and Sandeep Kulkarni |
| 16.35-16.45 | Closing remarks | |
