Areas of Interest
This workshop will focus on issues related to design, analysis and
testing of on-chip networks. We also look for new type of
NoC-based computing paradigms inspired by biological systems to
solve hard computational problems such as learning, recognition,
and complex decision making.
The topics of specific interest for the
workshop include, but are not limited to:
- Topologies selection and synthesis for NoCs and MPSoCs
- Routing algorithms and router micro-architectures
- QoS in on-chip communication
- Mapping of cores to NoC slots
- Power and energy issues
- Fault tolerance and reliability issues
- Memory architectures for NoC
- Dynamic on-chip network reconfiguration
- Modeling and evaluation of on-chip networks
- On-chip interconnection network simulators and emulators
- Analytical analysis methods for NoC performance and other properties
- Verification, debug and test of NoC
- 3D NoC architectures
- Emerging technologies and new design paradigms
- Industrial case studies of SoC designs using the NoC paradigm
- Heterogeneity
- NoC-based Brain-like computing device
- NoC-based platform for DNA sequencing
- HPC application and computer servers
Besides regular papers, papers
describing work in progress or incomplete but sound new
innovative ideas related to the workshop theme are also
encouraged.