Keynote talk by Chita Das, Pennsylvania State University, USA
General Information
The On-chip communication system represents one of the most important elements which determine the overall performance, cost, reliability, and energy consumption of a modern multi-processor system-on-chip (MPSoC). The role played by the communication infrastructure is predicted to become even more and more important in the future multi-core computing nodes. Several issues like communication errors (due to crosstalk, electromagnetic interference, inter-symbol interference, etc.), link latency, link power dissipation, etc., that were considered negligible in the previous technologies, are dominant in current and next generation MPSoC. In addition, as we approach the many-cores era, in which hundreds or thousands of communicating on-chip cores represent the basic scenario, scalability issues must be properly addressed to meet performance, power and reliability requirements which characterize future ambient intelligent applications. The network-on-chip (NoC) paradigm is considered as the most viable solution for designing on-chip communication systems wich will be able to handle all the above issues satisfactorily.
The goal of the workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.
Areas of Interest
This workshop focuses on issues related to design, analysis and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:
| Areas of Interest | |
|---|---|
| Topologies selection and synthesis for NoCs and MPSoCs | Modeling and evaluation of on-chip networks |
| Routing algorithms and router micro-architectures | On-chip interconnection network simulators and emulators |
| QoS in on-chip communication | Analytical analysis methods for NoC performance and other properties |
| Mapping of cores to NoC slots | Verification, debug and test of NoC |
| Power and energy issues | 3D NoC architectures |
| Fault tolerance and reliability issues | Emerging technologies and new design paradigms |
| Memory architectures for NoC | Industrial case studies of SoC designs using the NoC paradigm |
| Dynamic on-chip network reconfiguration | |
Submission Guidelines
Both research and application-oriented papers are welcome. All papers should be submitted electronically by EasyChair Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author.
Papers must be formatted in accordance to the ACM two column style. ACM Word or LaTeX style templates are available here. In addition, Authors should apply ACM Computing Classification categories and terms.
Submissions must be limited to 6 pages. Papers deviating significantly from these paper size and formatting rules may be rejected without review. If the authors wish a blind review to be performed, then the author's name and affiliation should be omitted in the submitted paper. In case of any questions please contact the workshop organizers.
Important Dates
| Paper submission deadline | |
|---|---|
| Author notification | |
| Camera-ready version due | November 5, 2011 |
| NoCArc Workshop | December 4, 2011 |
Organizers and Program Committee Chairs
 |
 |
|
| Maurizio Palesi | Shashi Kumar | |
| Kore University Italy |
Jönköping University Sweden |
Technical Program Committee
- Paul Ampadu, University of Rochester, USA
- Federico Angiolini, iNoCs, Switzerland
- Giuseppe Ascia, University of Catania, Italy
- Davide Bertozzi, University of Ferrara, Italy
- Claas Cornelius, University of Rostock, Germany
- Giorgos Dimitrakopoulos, University of West Macedonia, Greece
- José Flich Cardo, Universidad Politécnica de Valencia, Spain
- Chita R. Das, Pennsylvania State University, USA
- Natalie Enright Jerger, University of Toronto, Canada
- Martti Forsell, VTT, Finland
- Rickard Holsmark, Jönköping University, Sweden
- Axel Jantsch, Royal Institute of Technology, Sweden
- Yuho Jin, New Mexico State University, USA
- Shashi Kumar, Jönköping University, Sweden
- Zhonghai Lu, Royal Institute of Technology, Sweden
- Terrence Mak, Newcastle University, UK
- Radu Marculescu, Carnegie Mellon University, USA
- Umit Y. Ogras, Intel Corp., USA
- Juan Manuel Orduña Huertas, Universidad de Valencia, Spain
- Gianluca Palermo, Politecnico di Milano, Italy
- Maurizio Palesi, Kore University, Italy
- Partha P. Pande, Washington State University, USA
- Sudeep Pasricha, Colorado State University, USA
- Carlo Pistritto, STMicroelectronics, Italy
- Davide Patti, University of Catania, Italy
- Alberto Scandurra, STMicroelectronics, Italy
- Christof Teuscher, Portland State University, USA
- Xiaohang Wang, Zhejiang University, China
- Vittorio Zaccaria, Politecnico di Milano, Italy
Past Editions
| NoCArc 2010 | 3rd International Workshop on Network on Chip Architectures (NoCArc'10). Held in conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-43), December 4, 2010, Atlanta, Georgia, USA. |  |
| NoCArc 2009 | 2nd International Workshop on Network on Chip Architectures (NoCArc'09). Held in conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42), December 12, 2009, New York City, USA. |  |
| NoCArc 2008 | 1st International Workshop on Network on Chip Architectures (NoCArc'08). Held in conjunction with the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41), November 8, 2008, Lake Como, Italy. |  |
|
Follow us on facebook |
Call for Papers
PDF flyer of the call-for-papers.
Proceedings
The proceedings of NoCArc 2011 will be published in the ACM Digital Library.