Keynote Talks

How to Evaluate Efficient Deep Neural Network Approaches

Vivienne Sze, MIT

Architecting Chiplet-based Systems

Natalie Enright Jerger, University of Toronto


Unconventional computing and what it means for the future of interconnects

Marc Riedel, University of Minnesota — [DNA Computing]

Sudeep Pasricha, Colorado State University — [Photonic Computing and Interconnects]

Abu Sebastian, IBM Zurich — [Processing in Memory]

Rajeev Balasubramonian, University of Utah — [Accelerators]

Masoud Babaie, TU Delft — [Quantum Computing]

Baris Taskin, Drexel University — [Wireless Interconnects]


With the advancement in both computing architectures and process technology, many-core architectures can have thousands of cores into a single chip. This integration opens up a plethora of challenges, e.g., in terms of specialization and energy-focused implementations, and supports the spread of various applications and computational paradigms, ranging from multiprocessing to reconfigurable computing, from quantum computing to the emerging area of neuromorphic computing. Such a wild increase in the number of processing elements (PE) per chip, together with the growing architectural and workload heterogeneity, calls for efficient, versatile, scalable, and reliable communication infrastructures. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, the integration of a large number of PEs on a chip, or heterogeneous workloads. Novel techniques and architectures are needed to efficiently design and optimize the NoC and evaluate it at the network or system level.

The goal of NoCArc is to provide a forum for researchers to present and discuss innovative ideas and solutions related to the design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis, testing, and application of on-chip networks.