AREAS OF INTEREST

The workshop will focus on issues related to design, analysis and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:

NoC Architecture and Implementation

• Topologies, routing, flow control
• Managing QoS
• Reliability issues
• Security issues
• Design methodologies and tools

NoC Analysis, Optimization, and Verification

• Power, energy and thermal issues
• Benchmarking with NoC-based systems
• Modeling, simulation, and synthesis
• Verification, debug and test of
• Metrics and benchmarks

NoC Applications

• Mapping of applications onto NoCs
• Real and industrial NoC case studies
• NoCs for FPGAs, ASICs, CMPs and MPSoCs
• NoC designs for heterogeneous systems

NoC at System-level

• Design of memory subsystem
• NoC support for memory and cache access
• OS support for NoCs
• Programming models including shared memory, message passing and novel programming models
• Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks

Emerging NoC Technologies

• Wireless, Optical, and RF
• NoCs for 3D and 2.5D packages
• Approximate computing for NoC and NoC-based systems

Machine learning (ML) and NoC-based systems

• Interconnects for ML systems/accelerators
• Memory access for the NoC-based ML systems
• NoC-based ML algorithm design

Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.