Keynote Talks

Value-Based Deep Learning Hardware Acceleration

Andreas Moshovos, University of Toronto

3D Core-based SoC Testing for Low Power and TSV Count Minimization

Shih-Hsu Huang, Chung Yuan Christian University


With an advancement in both computing architectures and process technology, many-core architectures are going to have hundreds of cores into a single chip. It is expected that the integration becomes in the order of thousand cores within 2020 as stated by the International Technology Roadmap for Semiconductors, which benefits some emerging applications such as machine learning engine design. By increasing the number of processing elements (PEs) in System-on-Chip (SoC), there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, the communication delay and power consumption of global interconnections become the major bottleneck. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, and integration of a large number of PEs on a chip. Techniques and architectures are needed for efficiently design and optimize NoC and evaluate it at the network or system level. NoCs are also prone to failure where techniques are required to tolerate, verify and test. In addition, new technologies are emerging as wireless, optical, and RF and for 2.5D and 3D packages.

The goal of NoCArc is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis, and testing of on-chip networks.