Keynote Talk

3D Core-based SoC Testing for Low Power and 

TSV Count Minimization

Shih-Hsu Huang

Chung Yuan Christian University

Abstract

Three-dimensional (3D) core-based system-on-chips (SoCs) provides a promising solution to continue Moore’s law, but it also brings challenging problems, one of which is the 3D core-based SoC testing problem. Note that core tests include external tests and BIST (built-in-self-test). In addition to test time minimization, for a 3D IC, the allocation of wrapper chains (for external tests) and the allocation of BIST controllers are also important issues. In this talk, we will introduce two algorithms for 3D core-based SoC testing. First, we will present a 3D test wrapper chain synthesis algorithm (for external tests) to minimize the test time under a given TSV (through-silicon-vias) count constraint. Second, we will present a 3D BIST controller allocation algorithm to minimize the test time under a given power constraint. Benchmark data consistently show that the two proposed algorithms work well in practice.

Biography: Shih-Hsu Huang received the Ph.D. degree in Computer Science and Information Engineering from National Taiwan University, Taipei, Taiwan, in 1995. From 1995 to 2000, he was with Computer and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan, rising to the position of deputy manager of IC design department, responsible for the design of high performance ICs. In 2000, he joined the Department of Electronic Engineering, Chung Yuan Christian University, Taoyuan, Taiwan, as a faculty member, where he is currently a Full Professor. Moreover, in 2018, he received the Distinguished Professor Award from Chung Yuan Christian University.
From 2008 to 2012, Dr. Huang served as the chairman of the Department of Electronic Engineering, Chung Yuan Christian University. From 2013, he serves as the Director of the Research Center for Automotive Electronics and Reliability Research, Chung Yuan Christian University. In 2016, he served as the chair of CAD Contest at ICCAD. From 2017, he serves as the Vice Director of Program Office of AI Research, Ministry of Science and Technology, Taiwan. From 2018, he serves as the chair of ACM SIGDA Taiwan Chapter. His research interests include 3D SoC testing, low power design, and electronic design automation. Dr. Huang has published more than 70 technical papers and earned 9 patents. Dr. Huang is a senior member of IEEE.