Areas of Interest
The workshop will focus on issues related to design, analysis and
testing of on-chip networks. The topics of specific interest for
the workshop include, but are not limited to:
NoC Architecture and Implementation
- Topologies, routing, flow control
- Managing QoS
- Timing, synchronous/asynchronous communication
- Reliability issues
- Design methodologies and tools
- Signaling & circuit design for NoC links
NoC Analysis and Verification
- Power, energy and thermal issues
- Benchmarking and experience with NoC-based systems
- Modeling, simulation, and synthesis
- Verification, debug and test
- Metrics and benchmarks
NoC Application
- Mapping of applications onto NoCs
- NoC case studies, application-specific NoC design
- NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
- NoC designs for heterogeneous systems
On-Chip Communication Optimization
- Communication efficient algorithms
- Multi/many-core communication workload characterization and evaluation
- Energy efficient NoCs and energy minimization
NoC at System-level
- Design of memory subsystem
- NoC support for memory and cache access
- OS support for NoCs
- Programming models including shared memory, message passing and novel programming models
- Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks
Emerging NoC Technologies
- Wireless, Optical, and RF
- NoCs for 3D and 2.5D packages
Besides regular papers, papers
describing work in progress or incomplete but sound new
innovative ideas related to the workshop theme are also
encouraged.
