University of Catania
Department of Computer Science and Telecommunications Engineering (DIIT)
6, Viale Andrea Doria, 95125 Catania, Italy Phone: +39 095 738 2385,
Fax: +39 095 738 2397
Email: dpatti
[at] diit.unict.it
Sistemi Embedded per il Mobile
Multimedia: fare riferimento alla homepage del Prof. V.
Catania
Laboratorio di Calcolatori: fare
riferimento alla homepage del Prof. V.
Catania
Per eventuali dubbi riguardanti argomenti da me trattati, mandare una
email all'indirizzo: dpatti [at]
diit.unict.it
In alternativa, l'orario di ricevimento e' dalle 15 alle 16 il lunedi' e
il martedi' presso la stanza n.15 del nuovo edificio afferente al
Dipartimento di Ingegneria Informatica e delle Telecomunicazioni.
Research Summary
My research topics involve :
Design space exploration (DSE) strategies for parameterized embedded
architectures.
Instruction level parallelism of multimedia applications on VLIW based
architectures.
Network on Chip (NOC) systems
Computer Architectures for emerging Nanotechnologies
Projects
Epic ExplorerA
framework for the design space exploration of a paramerized architecture
based on a VLIW core. It includes area, power and performance estimators
and the implementation of several exploration algorithms presented in
literature.
NoximNetwork-on-Chip
simulator written in SystemC.
G. Ascia, V. Catania, M. Palesi, D. Patti. Implementation and Analysis
of a New Selection Strategy for Adaptive Routing in Networks-on-Chip.
Accepted for publication in IEEE Transactions on Computers.
V. Catania, M. Palesi, D. Patti. Reducing Complexity of Multi-objective Design
Space Exploration in VLIW-based Embedded Systems. Accepted for
publication in ACM Transactions on Architecture and Code Optimization.
V. Catania, M. Palesi, D. Patti. Analysis and Tools for the Design of VLIW
Embedded Systems in a Multi-objective Scenario. Accepted for
publication in Journal of Circuits Systems and Computers.
G.Ascia, V.Catania, A.G.Di Nuovo, M.Palesi, D.Patti Efficient Design
Space Exploration for Application Specific Systems-on-a-Chip. Journal
of Systems Architecture, Special Issue on Architectures, Modeling, and
Simulation for Embedded Processors, Volume 53, Issue 10, October 2007,
Pages 733-750.
Conference Papers
V. Catania, G. De Francisci Morales, A. G. Di Nuovo, M. Palesi, D. Patti.
High
Performance Computing for Embedded System Design: A Case Study. 11th
EUROMICRO Conference on Digital System Design, Architectures, Methods and
Tools, pp. 656-659, Sep. 3-5, 2008, Como, Italy.
G.Ascia, V.Catania, M.Palesi, D.Patti. Neighbors-on-Path: A New
Selection Strategy for On-Chip Networks. Fourth IEEE Workshop on
Embedded Systems for Real Time Multimedia, pp. 79-84. Seoul, Korea, October
26-27, 2006.
G.Ascia, V.Catania, A.Di Nuovo, M.Palesi, D.Patti. Fuzzy Decision
Making in Embedded System Design. International Conference on
Hardware-Software Codesign and System Synthesis, Seoul, Korea, October
22-25, 2006.
G.Ascia, V.Catania, A.Di Nuovo, M.Palesi, D.Patti. An Efficient
Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design.
Accepted for publication in IC-SAMOS: Embedded Computer Systems:
Architectures, Modeling, and Simulation. Samos, Greece, July 17-20, 2006.
G.Ascia, V.Catania, A.Di Nuovo, M.Palesi, D.Patti. A Multi-objective
Genetic Fuzzy Approach for Intelligent System-level Exploration in
Parameterized VLIW Processor Design. Accepted for publication in IEEE
Congress on Evolutionary Computation to be held in Sheraton Vancouver Wall
Centre, Vancouver, BC, Canada, July 2006.
G.Ascia, V.Catania, A.Di Nuovo, M.Palesi, D.Patti.Fuzzy Simulation to
Speedup Computer Design. In 4th Industrial Simulation Conference, pp.
285--289, Palermo, Italy, June 5--7 2006.
G.Ascia, V.Catania, M.Palesi, D.Patti. A New Selection Policy for
Adaptive Routing in Network on Chip. International Conference on
Electronics, Hardware, Wireless and Optical Communications. Madrid, Spain,
February 15-17, 2006.
G.Ascia, V.Catania, M.Palesi, D.Patti. Exploring Design Space of VLIW
Architectures. IEEE 16th International Conference on
Application-specific Systems, Architectures and Processors. Samos, Greece,
July 23-25, 2005.
G.Ascia, V.Catania, M.Palesi, D.Patti. Hyperblock Formation: A
Power/Energy Perspective for High Performance VLIW Architectures. IEEE
International Symposium on Circuits and Systems 2005, Japan, May 21-26,
2005.
G.Ascia, V.Catania, M.Palesi, D.Patti. A New
Selection Strategy for On-Chip Networks. Dipartimento di Ingegneria
Informatica e delle Telecomunicazioni, Universita' di Catania, Italy,
September 2006.
A quick glance on my other interests (always under construction):
Books: H. Hesse, M. Kundera, U. Eco, F. Nietzsche, G. Marquez, "Il
Malloppo" (Marcello Marchesi), "Godel, Escher, Bach" (Hofstadter), books on
prime numbers
Music: Radiohead, U2, Nine Inch Nails, Depeche Mode, CCCP/CSI, REM, De
Gregori, Smashing Pumpkins, Sonic Youth, Franco Battiato, Marlene Kuntz,
Blonde Red head, David Bowie, The Cure, Joy Division, Pink Floyd, 80's
dark/goth music, Indie rock bands etc...
Movies:too many to mention but, sometimes, I feel like: organizing a
"Fight Club" (Fincher), living in a David Lynch's shortfilm, being
"serious" like Nanni Moretti, wandering in a landscape from Wenders, (more
to come...)